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stm32: add clock configuration for stm32f412 to run at 96 MHz

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Add clock definition for stmf412. New stm32f4 chip variant will have to
define their own clock definitions.

BUG=b:37187312
TEST=`make BOARD=rose- j`

Change-Id: Ie053298d2f1255d7bc152f6018a674281bda7004
Reviewed-on: https://chromium-review.googlesource.com/487848
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
This commit is contained in:
Wei-Ning Huang
2017-05-07 14:42:46 +08:00
committed by chrome-bot
parent 8df3b161e9
commit 00da0f8c87
2 changed files with 23 additions and 5 deletions
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13
chip/stm32/clock-stm32f4.c
View File

@@ -91,22 +91,25 @@ void config_hispeed_clock(void)
pllinputclock = srcclock / plldiv;
/* PLL output clock: Must be 100-432MHz */
/* Valid values 50-432, we'll get 336MHz */
pllmult = (STM32F4_VCO_CLOCK + (pllinputclock / 2)) / pllinputclock;
vcoclock = pllinputclock * pllmult;
/* CPU/System clock: Below 180MHz */
/* We'll do 84MHz */
/* CPU/System clock */
systemclock = vcoclock / 4;
systemdivq = 1;
/* USB clock = 48MHz exactly */
usbdiv = (vcoclock + (STM32F4_USB_REQ / 2)) / STM32F4_USB_REQ;
assert(vcoclock / usbdiv == STM32F4_USB_REQ);
/* SYSTEM/I2S: same system clock */
i2sdiv = (vcoclock + (systemclock / 2)) / systemclock;
/* All IO clocks at 42MHz */
/* All IO clocks at STM32F4_IO_CLOCK
* For STM32F446: max 45 MHz
* For STM32F412: max 50 MHz
*/
/* AHB Prescalar */
ahbpre = 0x8; /* AHB = system clock / 2*/
ahbpre = 0x8; /* AHB = system clock / 2 */
/* NOTE: If apbXpre is not 0, timers are x2 clocked. RM0390 Fig. 13 */
apb1pre = 0; /* APB1 = AHB */
apb2pre = 0; /* APB2 = AHB */

15
chip/stm32/registers.h
View File

@@ -956,6 +956,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
#define STM32_RCC_CR_PLLON (1 << 24)
#define STM32_RCC_CR_PLLRDY (1 << 25)
#if defined(CHIP_VARIANT_STM32F446)
/* Required or recommended clocks for stm32f446 */
#define STM32F4_PLL_REQ 2000000
#define STM32F4_RTC_REQ 1000000
@@ -965,6 +966,20 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
#define STM32F4_HSI_CLOCK 16000000
#define STM32F4_LSI_CLOCK 32000
#elif defined(CHIP_VARIANT_STM32F412)
/* Required or recommended clocks for stm32f412 */
#define STM32F4_PLL_REQ 2000000
#define STM32F4_RTC_REQ 1000000
#define STM32F4_IO_CLOCK 48000000
#define STM32F4_USB_REQ 48000000
#define STM32F4_VCO_CLOCK 384000000
#define STM32F4_HSI_CLOCK 16000000
#define STM32F4_LSI_CLOCK 32000
#else
#error "No valid clocks defined"
#endif
#define STM32_RCC_PLLCFGR REG32(STM32_RCC_BASE + 0x04)
/* PLL Division factor */
#define PLLCFGR_PLLM_OFF 0