Add GPIO for PCH SRTCRST#

In case ctl decides to put it on a separate GPIO, he'll use PC7.  If
he doesn't, we can reclaim this GPIO.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=chrome-os-partner:7576
TEST=gpioget; signals should be present.  PCH_SRTCRSTn should be 1.

Change-Id: I4ca4437515d62c36d00fd28093ca41e806ce351a
This commit is contained in:
Randall Spangler
2012-05-07 19:04:39 -07:00
parent cbdd518422
commit 07e199e234
2 changed files with 5 additions and 3 deletions

View File

@@ -93,10 +93,11 @@ const struct gpio_info gpio_list[GPIO_COUNT] = {
{"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
{"PCH_RCINn", LM4_GPIO_Q, (1<<7), GPIO_OUT_LOW, NULL},
{"PCH_RSMRSTn", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL},
/* RTCRST# is unasserted by default so we don't clear the RTC wells
* in the PCH when the EC resets. */
/* RTCRST# (and SRTCRST# below) are unasserted by default so we don't
* clear the RTC wells in the PCH when the EC resets. */
{"PCH_RTCRSTn", LM4_GPIO_F, (1<<6), GPIO_OUT_HIGH, NULL},
{"PCH_SMIn", LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL},
{"PCH_SRTCRSTn", LM4_GPIO_C, (1<<7), GPIO_OUT_HIGH, NULL},
{"PCH_SUSACKn", LM4_GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL},
{"RADIO_DISABLE_WLAN", LM4_GPIO_D, (1<<0), GPIO_OUT_LOW, NULL},
{"RADIO_DISABLE_BT", LM4_GPIO_D, (1<<1), GPIO_OUT_LOW, NULL},

View File

@@ -162,8 +162,9 @@ enum gpio_signal {
GPIO_PCH_PWROK, /* PWROK / APWROK signals to PCH */
GPIO_PCH_RCINn, /* RCIN# signal to PCH */
GPIO_PCH_RSMRSTn, /* Reset PCH resume power plane logic */
GPIO_PCH_RTCRSTn, /* Reset PCH RTC wells */
GPIO_PCH_RTCRSTn, /* Reset PCH RTC well */
GPIO_PCH_SMIn, /* System management interrupt to PCH */
GPIO_PCH_SRTCRSTn, /* Reset PCH ME RTC well */
GPIO_PCH_SUSACKn, /* Acknowledge PCH SUSWARN# signal */
GPIO_RADIO_DISABLE_WLAN, /* Disable WLAN radio */
GPIO_RADIO_DISABLE_BT, /* Disable bluetooth radio */