nds32: enable GCC LTO

- We have more flash space to use with nds32 toolchain GCC6.3.0,
  so we enable a few console commands that were disabled previously.
  And we also enable LTO to reduce the size of FW image.

- Put "__wait_evt" function into ram_code section to
  fill the gap of flash and improving performance of code-fetch.

BUG=none
BRANCH=none
TEST=boot to kernel on reef_it8320.

Change-Id: I3b745ff80a57ef1163794864c39c22f7e1f86634
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/788712
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

board/reef_it8320/board.h

@@ -112,6 +112,7 @@
 #define CONFIG_LED_COMMON
 #define CONFIG_LID_SWITCH
 #define CONFIG_LOW_POWER_IDLE
+#define CONFIG_LTO
 #define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
 #define CONFIG_TABLET_MODE
 #define CONFIG_TEMP_SENSOR
@@ -143,14 +144,6 @@
 #undef CONFIG_SPI
 #undef CONFIG_UART_HOST
 
-/* TODO: There isn't enough space on flash before nds32 toolchain is updated */
-#undef CONFIG_CMD_HASH
-#undef CONFIG_CMD_I2C_XFER
-#undef CONFIG_CMD_IDLE_STATS
-#undef CONFIG_CMD_SLEEPMASK
-#undef CONFIG_CMD_TIMERINFO
-#undef CONFIG_CONSOLE_CMDHELP
-
 #undef CONFIG_UART_TX_BUF_SIZE
 #define CONFIG_UART_TX_BUF_SIZE 4096
 #undef CONFIG_UART_RX_BUF_SIZE

chip/it83xx/flash.c

@@ -6,6 +6,7 @@
 #include "common.h"
 #include "console.h"
 #include "flash.h"
+#include "flash_chip.h"
 #include "host_command.h"
 #include "system.h"
 #include "util.h"
@@ -15,7 +16,6 @@
 #include "shared_mem.h"
 #include "uart.h"
 
-const char __flash_dma_start;
 #define FLASH_DMA_START ((uint32_t) &__flash_dma_start)
 #define FLASH_DMA_CODE __attribute__((section(".flash_direct_map")))
 

chip/it83xx/flash_chip.h

@@ -0,0 +1,16 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_FLASH_CHIP_H
+#define __CROS_EC_FLASH_CHIP_H
+
+/*
+ * This symbol is defined in linker script and used to provide the begin
+ * address of the ram code section. With this address, we can enable a ILM
+ * (4K bytes static code cache) for ram code section.
+ */
+extern const char __flash_dma_start;
+
+#endif /* __CROS_EC_FLASH_CHIP_H */

core/nds32/__builtin.c

@@ -10,7 +10,7 @@
  * Returns one plus the index of the least significant 1-bit of x,
  * or if x is zero, returns zero.
  */
-int __ffssi2(int x)
+int __keep __ffssi2(int x)
 {
 	return 32 - __builtin_clz(x & -x);
 }

core/nds32/build.mk

@@ -15,5 +15,10 @@ $(call set-option,CROSS_COMPILE,$(CROSS_COMPILE_nds32),$(NDS32_DEFAULT_COMPILE))
 # CPU specific compilation flags
 CFLAGS_CPU+=-march=v3m -Os
 
+ifneq ($(CONFIG_LTO),)
+CFLAGS_CPU+=-flto
+LDFLAGS_EXTRA+=-flto
+endif
+
 core-y=cpu.o init.o panic.o task.o switch.o __muldi3.o math.o __builtin.o
 core-$(CONFIG_FPU)+=__libsoftfpu.o

core/nds32/task.c

@@ -256,7 +256,8 @@ int get_sw_int(void)
  *
  * Also includes emulation of software triggering interrupt vector
  */
-void __ram_code syscall_handler(int desched, task_id_t resched, int swirq)
+void __ram_code __keep syscall_handler(int desched, task_id_t resched,
+								int swirq)
 {
 	/* are we emulating an interrupt ? */
 	if (swirq) {
@@ -416,7 +417,7 @@ void end_irq_handler(void)
 #endif
 }
 
-static uint32_t __wait_evt(int timeout_us, task_id_t resched)
+static uint32_t __ram_code __wait_evt(int timeout_us, task_id_t resched)
 {
 	task_ *tsk = current_task;
 	task_id_t me = tsk - tasks;