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mec1322: Enable HW control of KBC aux buffer

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This turns on hardware controlled update of bit 5 (AUXOBF) in Keyboard
Status Read Register. Previously, this bit was in user-defined mode and
not reliable.

BUG=None
TEST=Tested that keyboard becomes functional on Braswell Ref Design.
BRANCH=None

Change-Id: I192383ebebb25a027d58da9fc1ef7f3bb3e8da66
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/263948
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Kevin K Wong <kevin.k.wong@intel.com>
This commit is contained in:
Shamile Khan
2015-02-09 14:35:24 -08:00
committed by ChromeOS Commit Bot
parent 55c739b9a4
commit 0c74006a0a
1 changed files with 4 additions and 0 deletions
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4
chip/mec1322/lpc.c
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@@ -212,6 +212,10 @@ static void setup_lpc(void)
/* Set up 8042 interface at 0x60/0x64 */
MEC1322_LPC_8042_BAR = 0x00608104;
/* Set up indication of Auxillary sts */
MEC1322_8042_KB_CTRL |= 1 << 7;
MEC1322_8042_ACT |= 1;
MEC1322_INT_ENABLE(15) |= ((1 << 13) | (1 << 14));
MEC1322_INT_BLK_EN |= 1 << 15;