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samus: Remove board version specific workarounds

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The next board revision will reset the ID to zero, so we
can no longer rely on the old versions for workarounds.

However those boards no longer work without modification due
to GPIO changes anyway so we can just remove the old code
and since there are no more workarounds left remove the board
version enum since it is no longer used.

BUG=chrome-os-partner:32895
BRANCH=samus
TEST=build and boot on samus EVT2

Change-Id: I3f76cda6b533fe195a743baa7981a0e67d371313
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229003
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
Duncan Laurie
2014-11-11 07:47:21 -08:00
committed by chrome-internal-fetch
parent 73e182a443
commit 0f4a2c333c
2 changed files with 23 additions and 53 deletions
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10
board/samus/board.h
View File

@@ -166,16 +166,6 @@ enum als_id {
ALS_COUNT,
};
/* Known board versions for system_get_board_version(). */
enum board_version {
BOARD_VERSION_PROTO_1_9 = 0,
BOARD_VERSION_PROTO_2_A = 1,
BOARD_VERSION_PROTO_2_B = 2,
BOARD_VERSION_EVT = 3,
BOARD_VERSION_EVT2 = 4,
BOARD_VERSION_EVT3 = 5,
};
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN

66
board/samus/power_sequence.c
View File

@@ -98,13 +98,11 @@ static void chipset_reset_rtc(void)
* Assert RTCRST# to the PCH long enough for it to latch the
* assertion and reset the internal RTC backed state.
*/
if (system_get_board_version() >= BOARD_VERSION_EVT) {
CPRINTS("Asserting RTCRST# to PCH");
gpio_set_level(GPIO_PCH_RTCRST_L, 0);
udelay(100);
gpio_set_level(GPIO_PCH_RTCRST_L, 1);
udelay(10 * MSEC);
}
CPRINTS("Asserting RTCRST# to PCH");
gpio_set_level(GPIO_PCH_RTCRST_L, 0);
udelay(100);
gpio_set_level(GPIO_PCH_RTCRST_L, 1);
udelay(10 * MSEC);
}
void chipset_reset(int cold_reset)
@@ -260,45 +258,27 @@ enum power_state power_handle_state(enum power_state state)
gpio_set_level(GPIO_PCH_DPWROK, 1);
/*
* Proto2B boards added EC control of RSMRST which allows
* the sequencing to properly wait for SLP_SUS before
* enabling the 1.05V rail. Prior to this the sequencing
* had board specific timing requirements that needed the
* 1.05V rail to be brought up just after DPWROK assertion.
* Wait for SLP_SUS before enabling 1.05V rail.
*/
if (system_get_board_version() <= BOARD_VERSION_PROTO_2_A) {
CPRINTS("Proto2A board, using alternate sequencing");
/* Enable PP1050 rail. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050 |
IN_PCH_SLP_SUS_DEASSERTED)) {
CPRINTS("timeout waiting for PP1050/SLP_SUS");
chipset_force_g3();
}
} else {
if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
CPRINTS("timeout waiting for SLP_SUS deassert");
chipset_force_g3();
return POWER_G3;
}
/* Enable PP1050 rail. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050)) {
CPRINTS("timeout waiting for PP1050");
chipset_force_g3();
return POWER_G3;
}
/* Deassert RSMRST# */
gpio_set_level(GPIO_PCH_RSMRST_L, 1);
if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
CPRINTS("timeout waiting for SLP_SUS deassert");
chipset_force_g3();
return POWER_G3;
}
/* Enable PP1050 rail. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050)) {
CPRINTS("timeout waiting for PP1050");
chipset_force_g3();
return POWER_G3;
}
/* Deassert RSMRST# */
gpio_set_level(GPIO_PCH_RSMRST_L, 1);
/* Wait 5ms for SUSCLK to stabilize */
msleep(5);