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samus: Rename PCH_HDA_SDO GPIO
This was inverted in the schematic, but is also connected to a FET and is expected to be driven. However it is not working properly so for now leave the GPIO as an input. BUG=chrome-os-partner:31833 BRANCH=None TEST=build and boot on samus EVT Change-Id: I10d6a40b1102df866a9d32c52a9f67eb24c3ce7a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/216942 Reviewed-by: Alec Berg <alecaberg@chromium.org>
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chrome-internal-fetch
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commit
10042d9c5c
@@ -46,6 +46,7 @@ GPIO(USB1_STATUS_L, E, 6, GPIO_INPUT, NULL) /* USB charger port 1 status output
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GPIO(USB2_OC_L, E, 0, GPIO_INPUT, NULL) /* USB port overcurrent warning */
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GPIO(USB2_STATUS_L, D, 7, GPIO_INPUT, NULL) /* USB charger port 2 status output */
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GPIO(PD_IN_RW, A, 5, GPIO_INPUT, NULL) /* PD is in RW */
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GPIO(PCH_HDA_SDO_L, G, 1, GPIO_INPUT, NULL) /* HDA_SDO signal to PCH to disable ME */
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/* Outputs; all unasserted by default except for reset signals */
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GPIO(CPU_PROCHOT, B, 1, GPIO_OUT_LOW, NULL) /* Force CPU to think it's overheated */
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@@ -68,11 +69,6 @@ GPIO(LIGHTBAR_RESET_L, J, 2, GPIO_ODR_LOW, NULL) /* Reset lightbar controlle
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GPIO(PCH_DPWROK, G, 0, GPIO_OUT_LOW, NULL) /* Indicate when VccDSW is good */
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GPIO(PCH_RSMRST_L, C, 4, GPIO_OUT_LOW, NULL) /* Reset PCH resume power plane logic */
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GPIO(PCH_RTCRST_L, J, 1, GPIO_ODR_HIGH, NULL) /* Reset PCH RTC well */
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/*
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* HDA_SDO is technically an output, but we need to leave it as an
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* input until we drive it high. So can't use open-drain (HI_Z).
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*/
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GPIO(PCH_HDA_SDO, G, 1, GPIO_INPUT, NULL) /* HDA_SDO signal to PCH; when high, ME ignores security descriptor */
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GPIO(PCH_WAKE_L, F, 0, GPIO_ODR_HIGH, NULL) /* Wake signal from EC to PCH */
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GPIO(PCH_NMI_L, F, 2, GPIO_ODR_HIGH, NULL) /* Non-maskable interrupt pin to PCH */
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GPIO(PCH_PWRBTN_L, H, 0, GPIO_ODR_HIGH, NULL) /* Power button output to PCH */
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