Fizz: add CONFIG_BOARD_HAS_RTC_RESET

This patch resets the RTC of the SoC when the system doesn't leave
S5. If it fails 5 times, the system will go back to and stay in G3.

BUG=b:79323716
BRANCH=fizz
TEST=Boot Fizz differently:
1. AC plug-in
2. Power button press
3. reboot EC command
4. servo reset button
5. Recovery mode

Change-Id: I728c99c342fb888600599acbe25f72a478ccf948
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1020583
Reviewed-on: https://chromium-review.googlesource.com/1089035
Reviewed-by: Duncan Laurie <dlaurie@google.com>

board/chell/board.h

@@ -223,9 +223,6 @@ extern const int keyboard_factory_scan_pins_used;
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
 
-/* Reset RTC */
-void board_rtc_reset(void);
-
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BOARD_H */

board/fizz/board.c

@@ -689,3 +689,11 @@ int fan_percent_to_rpm(int fan, int pct)
 	}
 	return get_custom_rpm(fan, pct, oem_id);
 }
+
+void board_rtc_reset(void)
+{
+	CPRINTS("Asserting RTCRST# to PCH");
+	gpio_set_level(GPIO_PCH_RTCRST, 1);
+	udelay(100);
+	gpio_set_level(GPIO_PCH_RTCRST, 0);
+}

board/fizz/board.h

@@ -18,6 +18,7 @@
 /* EC */
 #define CONFIG_ADC
 #define CONFIG_BOARD_VERSION_CBI
+#define CONFIG_BOARD_HAS_RTC_RESET
 #define CONFIG_CRC8
 #define CONFIG_CEC
 #define CONFIG_CROS_BOARD_INFO

board/nocturne/board.h

@@ -230,7 +230,6 @@ enum sensor_id {
 
 void base_pwr_fault_interrupt(enum gpio_signal s);
 int board_get_version(void);
-void board_rtc_reset(void);
 
 /* Reset all TCPCs. */
 void board_reset_pd_mcu(void);

power/intel_x86.h

@@ -33,4 +33,9 @@ enum power_state chipset_force_g3(void);
  */
 enum power_state common_intel_x86_power_handle_state(enum power_state state);
 
+/**
+ * Reset RTC
+ */
+void board_rtc_reset(void);
+
 #endif /* __CROS_EC_INTEL_X86_H */