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chip: it83xx: it8320 compatibility

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To ensure it8320's compatibility on the LPC platform, we need to
disable SPI slave interface (default enabled) so that LPC module
will function normally.

Signed-off-by: Dino Li <dino.li@ite.com.tw>

BRANCH=none
BUG=none
TEST=LPC module of it8320 works normally.

Change-Id: I259651b32f41ebae498e13bf07ebb68e5e520058
Reviewed-on: https://chromium-review.googlesource.com/328142
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Dino Li
2016-02-18 11:24:02 +08:00
committed by chrome-bot
parent 5efbecb770
commit 15f6889c66
2 changed files with 3 additions and 0 deletions
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2
chip/it83xx/lpc.c
View File

@@ -566,6 +566,8 @@ static void lpc_init(void)
{
enum ec2i_message ec2i_r;
/* SPI slave interface is disabled */
IT83XX_GCTRL_SSCR = 0;
/*
* DLM 52k~56k size select enable.
* For mapping LPC I/O cycle 800h ~ 9FFh to DLM 8D800 ~ 8D9FF.

1
chip/it83xx/registers.h
View File

@@ -682,6 +682,7 @@ enum clock_gate_offsets {
#define IT83XX_GCTRL_EPLR REG8(IT83XX_GCTRL_BASE+0x37)
#define IT83XX_GCTRL_IVTBAR REG8(IT83XX_GCTRL_BASE+0x41)
#define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44)
#define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A)
#define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i)
#define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE+0xA0+i)
#define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i)