baytrail: clear the pmc wake status registers

The PMC in baytrail maintains an additional set
wake status in memory-mapped registers. If these
bits aren't cleared the device won't be able to
go to S5 or S3 without being immediately woken up.
Therefore clear these registers.

BUG=chrome-os-partner:24913
BRANCH=rambi,squawks
TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work
     correctly.

Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181984
Reviewed-on: http://review.coreboot.org/5034
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/soc/intel/baytrail/baytrail/pmc.h

@@ -270,6 +270,7 @@ uint16_t clear_pm1_status(void);
 uint32_t clear_tco_status(void);
 uint32_t clear_gpe_status(void);
 uint32_t clear_alt_status(void);
+void clear_pmc_status(void);
 void enable_smi(uint32_t mask);
 void disable_smi(uint32_t mask);
 void enable_pm1(uint16_t events);

src/soc/intel/baytrail/pmutil.c

@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <console/console.h>
 
+#include <baytrail/iomap.h>
 #include <baytrail/lpc.h>
 #include <baytrail/pci_devs.h>
 #include <baytrail/pmc.h>
@@ -348,3 +349,16 @@ uint32_t clear_alt_status(void)
 {
 	return print_alt_sts(reset_alt_status());
 }
+
+void clear_pmc_status(void)
+{
+	uint32_t prsts;
+	uint32_t gen_pmcon1;
+
+	prsts = read32(PMC_BASE_ADDRESS + PRSTS);
+	gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
+
+	/* Clear the status bits. */
+	write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1);
+	write32(PMC_BASE_ADDRESS + PRSTS, prsts);
+}

src/soc/intel/baytrail/smm.c

@@ -62,6 +62,7 @@ void southcluster_smm_clear_state(void)
 	clear_tco_status();
 	clear_gpe_status();
 	clear_alt_status();
+	clear_pmc_status();
 }
 
 static void southcluster_smm_route_gpios(void)