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rambi: Support USB port power control

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Rambi shares several of the control signals (CTL1, ILIM_SEL) between
both ports, and hard-wires some of the others (CTL2, CTL3).  It still
has separate enable lines for each port.

BUG=chrome-os-partner:18343
BRANCH=none
TEST=boot system; gpioget shows (in part)

  1  USB_CTL1
  0  USB_ILIM_SEL
  1  USB1_ENABLE
  1  USB2_ENABLE

  Then do 'apshutdown' and gpioget shows

  1  USB_CTL1
  0  USB_ILIM_SEL
  0  USB1_ENABLE
  0  USB2_ENABLE

Change-Id: Ib3d321ca2b0aa7dce08ddd6633810a75641bc9a8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This commit is contained in:
Randall Spangler
2013-10-18 16:44:06 -07:00
committed by chrome-internal-fetch
parent d9530449fd
commit 1d6687429c
2 changed files with 15 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/rambi/board.h
View File

@@ -26,6 +26,7 @@
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_G781
#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PP3300_DX_EN
#define CONFIG_USB_PORT_POWER_SMART
#define CONFIG_WIRELESS
/* TODO(rspangler): port these to Rambi, or remove if not needed */
@@ -38,7 +39,6 @@
#define CONFIG_CHARGER_INPUT_CURRENT 4032 /* mA, about half max */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input sensor resistor, mOhm */
#define CONFIG_USB_PORT_POWER_DUMB
#endif
#ifndef __ASSEMBLER__

14
common/usb_port_power_smart.c
View File

@@ -34,6 +34,14 @@ static uint8_t charge_mode[USB_CHARGE_PORT_COUNT];
static void usb_charge_set_control_mode(int port_id, int mode)
{
#ifdef BOARD_rambi
/*
* Rambi has only a single shared control signal, so the last mode set
* to either port wins. Also, only CTL1 can be set; the other pins
* are hard-wired.
*/
gpio_set_level(GPIO_USB_CTL1, mode & 0x4);
#else
if (port_id == 0) {
gpio_set_level(GPIO_USB1_CTL1, mode & 0x4);
gpio_set_level(GPIO_USB1_CTL2, mode & 0x2);
@@ -43,6 +51,7 @@ static void usb_charge_set_control_mode(int port_id, int mode)
gpio_set_level(GPIO_USB2_CTL2, mode & 0x2);
gpio_set_level(GPIO_USB2_CTL3, mode & 0x1);
}
#endif
}
static void usb_charge_set_enabled(int port_id, int en)
@@ -55,10 +64,15 @@ static void usb_charge_set_enabled(int port_id, int en)
static void usb_charge_set_ilim(int port_id, int sel)
{
#ifdef BOARD_rambi
/* Rambi has a shared ILIM_SEL signal too */
gpio_set_level(GPIO_USB_ILIM_SEL, sel);
#else
if (port_id == 0)
gpio_set_level(GPIO_USB1_ILIM_SEL, sel);
else
gpio_set_level(GPIO_USB2_ILIM_SEL, sel);
#endif
}
static void usb_charge_all_ports_on(void)