npcx: unset ESPIRSTWE bit to prevent ec cannot enter low power mode

This CL fixed the issue that ec cannot enter low power mode, which
increases more power consumption in s5, by not setting ESPIRSTWE bit.

For more detail, please see the npcx5's errata rev1_7, No.2.21.

BRANCH=none
BUG=b:69351155
TEST=No build errors for "make buildall".
TEST=build and flash soraka, run commands to read the power consumption:
  dut-control pp3300_dsw_ec_cfg_reg:0x7327k
  dut-control pp3300_dsw_ec_mw -t 20 | grep "@@"
the average power consumption measured reduces from 42.x to 10.x mw.
TEST=do cold reboot stress test for 4 hours and no symptom occurred.

Change-Id: Ic6fd7fe14ae8acaefd4e1a99ca1625254f67d708
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/778709
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>

chip/npcx/espi.c

@@ -86,7 +86,7 @@ static const struct vwevsm_config_t espi_out_list[] = {
 /* eSPI interrupts used in MIWU */
 static const struct host_wui_item espi_vw_int_list[] = {
 	/* ESPI_RESET  */
-	{MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_RISING},
+	{MIWU_TABLE_0, MIWU_GROUP_5, 5, MIWU_EDGE_FALLING},
 	/* SLP_S3 */
 	{MIWU_TABLE_2, MIWU_GROUP_1, 0, MIWU_EDGE_ANYING},
 	/* SLP_S4 */

chip/npcx/registers.h

@@ -1577,7 +1577,7 @@ enum ITIM16_MODULE_T {
 #define ESPIWE_VW                        ESPIWE_VWUPD
 /* eSPI  Wake-up enable for Generic */
 #define ESPIWE_GENERIC                   (ESPIWE_IBRST | ESPIWE_CFGUPD | \
-					  ESPIWE_BERR | ESPIWE_ESPIRST)
+					  ESPIWE_BERR)
 /* Macro functions for eSPI VW */
 #define ESPI_VWEVMS_NUM                  12
 #define ESPI_VWEVSM_NUM                  10