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nuc: Remove unnecessary NPCX_EC_FLASH_SIZE definition in npcx.

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Remove NPCX_EC_FLASH_SIZE definition and replace it with CONFIG_FLASH_SIZE.
Due to inconsistence between NPCX_EC_FLASH_SIZE and CONFIG_FLASH_SIZE,
some flash commands such as flasherase will cause unexpected results.

Modified drivers:
1. config_flash_layout.h: Remove NPCX_EC_FLASH_SIZE definition.
2. flash.c: Replace NPCX_EC_FLASH_SIZE with CONFIG_FLASH_SIZE.

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: Idca286eef5bb014d5c4cd689c39635e09f40ee03
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/307004
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Mulin Chao
2015-10-19 11:54:42 +08:00
committed by chrome-bot
parent ab24609287
commit 228c1687ef
2 changed files with 11 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
chip/npcx/config_flash_layout.h
View File

@@ -20,12 +20,6 @@
#define CONFIG_MAPPED_STORAGE_BASE 0x64000000
#undef CONFIG_FLASH_PSTATE
/*
* On NPCX, the first 256KB of external SPI storage belongs to the EC,
* regardless of the actual size of external SPI.
*/
#define NPCX_EC_FLASH_SIZE 0x40000
#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000
#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000

23
chip/npcx/flash.c
View File

@@ -210,13 +210,12 @@ static int reg_to_protect(uint8_t sr1, uint8_t sr2, unsigned int *start,
*len = size * blocks;
/* Determine bottom/top of memory to protect */
*start = tb ? 0 :
(NPCX_EC_FLASH_SIZE - *len) % NPCX_EC_FLASH_SIZE;
*start = tb ? 0 : (CONFIG_FLASH_SIZE - *len);
/* Reverse computations if complement set */
if (cmp) {
*start = (*start + *len) % NPCX_EC_FLASH_SIZE;
*len = NPCX_EC_FLASH_SIZE - *len;
*start = *start + *len;
*len = CONFIG_FLASH_SIZE - *len;
}
/*
@@ -261,19 +260,19 @@ static int protect_to_reg(unsigned int start, unsigned int len,
return EC_ERROR_INVAL;
/* Invalid data */
if ((start && !len) || start + len > NPCX_EC_FLASH_SIZE)
if ((start && !len) || start + len > CONFIG_FLASH_SIZE)
return EC_ERROR_INVAL;
/* Set complement bit based on whether length is power of 2 */
if ((len & (len - 1)) != 0) {
cmp = 1;
start = (start + len) % NPCX_EC_FLASH_SIZE;
len = NPCX_EC_FLASH_SIZE - len;
start = start + len;
len = CONFIG_FLASH_SIZE - len;
}
/* Set bottom/top bit based on start address */
/* Do not set if len == 0 or len == NPCX_EC_FLASH_SIZE */
if (!start && (len % NPCX_EC_FLASH_SIZE))
/* Do not set if len == 0 or len == CONFIG_FLASH_SIZE */
if (!start && (len % CONFIG_FLASH_SIZE))
tb = 1;
/* Set sector bit and determine block length based on protect length */
@@ -333,7 +332,7 @@ int flash_set_status_for_prot(int reg1, int reg2)
int flash_check_prot_range(unsigned int offset, unsigned int bytes)
{
/* Invalid value */
if (offset + bytes > NPCX_EC_FLASH_SIZE)
if (offset + bytes > CONFIG_FLASH_SIZE)
return EC_ERROR_INVAL;
/* Check if ranges overlap */
if (MAX(addr_prot_start, offset) < MIN(addr_prot_start +
@@ -354,7 +353,7 @@ int flash_check_prot_reg(unsigned int offset, unsigned int bytes)
sr2 = flash_get_status2();
/* Invalid value */
if (offset + bytes > NPCX_EC_FLASH_SIZE)
if (offset + bytes > CONFIG_FLASH_SIZE)
return EC_ERROR_INVAL;
/* Compute current protect range */
@@ -377,7 +376,7 @@ int flash_write_prot_reg(unsigned int offset, unsigned int bytes)
uint8_t sr2 = flash_get_status2();
/* Invalid values */
if (offset + bytes > NPCX_EC_FLASH_SIZE)
if (offset + bytes > CONFIG_FLASH_SIZE)
return EC_ERROR_INVAL;
/* Compute desired protect range */