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Tegra: fix logic to calculate GICD_ISPENDR register address

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This patch uses GICD_BASE to calculate the GICD_ISPENDR regsiter address
in the platform's 'plat_crash_print_regs' routine.

Reported by: Seth Eatinger <seatinger@nvidia.com>

Change-Id: Ic7be29abc781f475ad25b59582ae60a0a2497377
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
2016-08-23 14:01:19 -07:00
parent 5b5928e834
commit 23cd470f86
1 changed files with 2 additions and 1 deletions
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3
plat/nvidia/tegra/include/plat_macros.S
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@@ -52,7 +52,7 @@ spacer:
*/
.macro plat_crash_print_regs
mov_imm x16, TEGRA_GICC_BASE
cbz x16, 1f
/* gicc base address is now in x16 */
adr x6, gicc_regs /* Load the gicc reg list to x6 */
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
@@ -63,6 +63,7 @@ spacer:
bl str_in_crash_buf_print
/* Print the GICD_ISPENDR regs */
mov_imm x16, TEGRA_GICD_BASE
add x7, x16, #GICD_ISPENDR
adr x4, gicd_pend_reg
bl asm_print_str