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Pulse EC_ENTERING_RW instead of just leaving it high

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The Silego chip has a 50k pulldown which will leak power if we leave
EC_ENTERING_RW high.  We don't need to leave it high, because once the
latch in the Silego gets set it ignores this signal.  This is ~100uA,
so it only really matters in S5 on pit (since x86 boards and spring
both hibernate in S5).

BUG=chrome-os-partner:20757
BRANCH=none
TEST=probe ec_in_rw signal before/after sysjump

Change-Id: Ib6b09cfc7718b35e4e93c952c3098c08d53572e2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62133
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Randall Spangler
2013-07-16 10:23:25 -07:00
committed by ChromeBot
parent 298a7276c2
commit 245275f4b6
1 changed files with 8 additions and 1 deletions
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9
common/system_common.c
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@@ -16,6 +16,7 @@
#include "panic.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "uart.h"
#include "util.h"
#include "version.h"
@@ -301,9 +302,15 @@ static void jump_to_image(uintptr_t init_addr)
/*
* Jumping to any image asserts the signal to the Silego chip that that
* EC is not in read-only firmware. (This is not technically true if
* jumping from RO -> RO, but that's not a meaningful use case...)
* jumping from RO -> RO, but that's not a meaningful use case...).
*
* Pulse the signal long enough to set the latch in the Silego, then
* drop it again so we don't leak power through the pulldown in the
* Silego.
*/
gpio_set_level(GPIO_ENTERING_RW, 1);
usleep(MSEC);
gpio_set_level(GPIO_ENTERING_RW, 0);
/* Flush UART output unless the UART hasn't been initialized yet */
if (uart_init_done())