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common: Add software CTZ implementation when needeed

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CTZ - Count Trailing Zero - is not implemented in hardware on cortex0 or
nds32.

Used in ST sensor drivers.

BUG=none
BRANCH=none
TEST=compile

Change-Id: I2d62fd60f05169189b24ba2a3308bec69ed9de9c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/767609
Commit-Ready: Ely Vazquez <nadia198877@gmail.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Gwendal Grignou
2017-11-07 13:54:06 -08:00
committed by chrome-bot
parent 26090a142b
commit 2590ce9538
5 changed files with 35 additions and 2 deletions
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1
common/build.mk
View File

@@ -91,6 +91,7 @@ common-$(CONFIG_SHA1)+= sha1.o
common-$(CONFIG_SHA256)+=sha256.o
common-$(CONFIG_SMBUS)+= smbus.o
common-$(CONFIG_SOFTWARE_CLZ)+=clz.o
common-$(CONFIG_SOFTWARE_CTZ)+=ctz.o
common-$(CONFIG_CMD_SPI_XFER)+=spi_commands.o
common-$(CONFIG_SPI_FLASH)+=spi_flash.o spi_flash_reg.o
common-$(CONFIG_SPI_FLASH_REGS)+=spi_flash_reg.o

27
common/ctz.c Normal file
View File

@@ -0,0 +1,27 @@
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Software emulation for CTZ instruction
*/
#include "common.h"
/**
* Count trailing zeros
*
* @param x non null integer.
* @return the number of trailing 0-bits in x,
* starting at the least significant bit position.
*
* Using a de Brujin sequence, as documented here:
* http://graphics.stanford.edu/~seander/bithacks.html#ZerosOnRightMultLookup
*/
int __keep __ctzsi2(int x)
{
static const uint8_t MulDeBruijnBitPos[32] = {
0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8,
31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9
};
return MulDeBruijnBitPos[((uint32_t)((x & -x) * 0x077CB531U)) >> 27];
}

3
core/cortex-m0/config_core.h
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@@ -10,8 +10,9 @@
#define BFD_ARCH arm
#define BFD_FORMAT "elf32-littlearm"
/* Emulate the CLZ instruction since the CPU core is lacking support */
/* Emulate the CLZ/CTZ instructions since the CPU core is lacking support */
#define CONFIG_SOFTWARE_CLZ
#define CONFIG_SOFTWARE_CTZ
#define CONFIG_SOFTWARE_PANIC
#endif /* __CROS_EC_CONFIG_CORE_H */

3
core/nds32/config_core.h
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@@ -13,9 +13,10 @@
#define CONFIG_SOFTWARE_PANIC
/*
* The Andestar v3m architecture has no CLZ instruction (contrary to v3),
* The Andestar v3m architecture has no CLZ/CTZ instructions (contrary to v3),
* so let's use the software implementation.
*/
#define CONFIG_SOFTWARE_CLZ
#define CONFIG_SOFTWARE_CTZ
#endif /* __CROS_EC_CONFIG_CORE_H */

3
include/config.h
View File

@@ -2141,6 +2141,9 @@
/* Emulate the CLZ (Count Leading Zeros) in software for CPU lacking support */
#undef CONFIG_SOFTWARE_CLZ
/* Emulate the CLZ (Count Trailing Zeros) in software for CPU lacking support */
#undef CONFIG_SOFTWARE_CTZ
/* Support smbus interface */
#undef CONFIG_SMBUS