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kevin / gru: Keep SPIP module disabled in S3 / S5

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SPIP is only used in S0, so keep the module disabled in lower power
states. Disabling SPIP through spi_enable() will also restore our CS pin
to ODR_HIGH.

BUG=chrome-os-partner:56860
BRANCH=None
TEST=Verify SPIP is functional on initial power-up, sysjump, and on
apshutdown / re-power-on. Also verify GPIO_SPI_SENSOR_CS_L goes low in
S5.

Change-Id: I14d845895a43700d2133a532cff63d08f0e64018
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380215
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2016-09-01 13:28:02 -07:00
committed by chrome-bot
parent 2629e96b57
commit 269b8e71e4
1 changed files with 18 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
board/kevin/board.c
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@@ -280,6 +280,22 @@ int pd_snk_is_vbus_provided(int port)
return bd99955_is_vbus_provided(bd99955_port);
}
static void board_spi_enable(void)
{
spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
}
DECLARE_HOOK(HOOK_CHIPSET_RESUME,
board_spi_enable,
MOTION_SENSE_HOOK_PRIO - 1);
static void board_spi_disable(void)
{
spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_SUSPEND,
board_spi_disable,
MOTION_SENSE_HOOK_PRIO + 1);
static void board_init(void)
{
/* Enable TCPC alert interrupts */
@@ -294,9 +310,8 @@ static void board_init(void)
gpio_enable_interrupt(GPIO_AP_OVERTEMP);
/* Sensor Init */
gpio_config_module(MODULE_SPI_MASTER, 1);
spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
CPRINTS("Board using SPI sensors");
if (system_jumped_to_this_image() && chipset_in_state(CHIPSET_STATE_ON))
board_spi_enable();
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);