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power: rk3399: Add power-down sequencing

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Power-down sequence in reverse order of power-up, with delays extended
to 10ms, to allow rails extra time to decay.

BUG=chrome-os-partner:54159
BRANCH=None
TEST=Manual on gru. Verify repeated `powerbtn` commands on console
boot + power-down the SOC.

Change-Id: I2e8fb39f8f900e56deef6b386bae1c336aa1f963
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351520
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2016-06-10 09:57:03 -07:00
committed by chrome-bot
parent 1afa7935c4
commit 26da26a4f9
1 changed files with 37 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

88
power/rk3399.c
View File

@@ -40,36 +40,6 @@
/* All inputs in the right state for S0 */
#define IN_ALL_S0 (IN_PGOOD_S0 | IN_SUSPEND_DEASSERTED)
static const struct power_signal_info power_control_outputs[] = {
{ GPIO_AP_CORE_EN, 1 },
{ GPIO_LPDDR_PWR_EN, 1 },
{ GPIO_PPVAR_CLOGIC_EN, 1 },
{ GPIO_PPVAR_LOGIC_EN, 1 },
{ GPIO_PP900_AP_EN, 1 },
{ GPIO_PP900_DDRPLL_EN, 1 },
{ GPIO_PP900_PLL_EN, 1 },
{ GPIO_PP900_PMU_EN, 1 },
{ GPIO_PP900_USB_EN, 1 },
{ GPIO_PP900_PCIE_EN, 1 },
{ GPIO_PP1800_SENSOR_EN_L, 0 },
{ GPIO_PP1800_LID_EN_L, 0 },
{ GPIO_PP1800_PMU_EN_L, 0 },
{ GPIO_PP1800_AP_AVDD_EN_L, 0 },
{ GPIO_PP1800_USB_EN_L, 0 },
{ GPIO_PP1800_S0_EN_L, 0 },
{ GPIO_PP1800_SIXAXIS_EN_L, 0 },
{ GPIO_PP3300_TRACKPAD_EN_L, 0 },
{ GPIO_PP3300_USB_EN_L, 0 },
{ GPIO_PP3300_S0_EN_L, 0 },
{ GPIO_PP5000_EN, 1 },
{ GPIO_SYS_RST_L, 0 },
};
static int forcing_shutdown;
void chipset_force_shutdown(void)
@@ -95,20 +65,6 @@ void chipset_reset(int cold_reset)
gpio_set_level(GPIO_SYS_RST_L, 1);
}
static void chipset_force_g3(void)
{
int i;
const struct power_signal_info *output_signal;
/* Force all signals to their G3 states */
CPRINTS("forcing G3");
for (i = 0; i < ARRAY_SIZE(power_control_outputs); ++i) {
output_signal = &power_control_outputs[i];
gpio_set_level(output_signal->gpio,
!output_signal->level);
}
}
enum power_state power_chipset_init(void)
{
if (system_jumped_to_this_image()) {
@@ -118,7 +74,6 @@ enum power_state power_chipset_init(void)
return POWER_S0;
}
chipset_force_g3();
wireless_set_state(WIRELESS_OFF);
#ifdef BOARD_GRU
/* TODO: Enable CONFIG_USB_PORT_POWER_SMART */
@@ -244,13 +199,24 @@ enum power_state power_handle_state(enum power_state state)
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SUSPEND);
#ifdef BOARD_GRU
gpio_set_level(GPIO_USB_A_CHARGE_EN, 0);
gpio_set_level(GPIO_USB_A_EN, 0);
#endif
/* Suspend wireless */
wireless_set_state(WIRELESS_SUSPEND);
#ifdef BOARD_GRU
gpio_set_level(GPIO_USB_A_EN, 0);
gpio_set_level(GPIO_USB_A_CHARGE_EN, 0);
#endif
gpio_set_level(GPIO_PP1800_SENSOR_EN_L, 1);
gpio_set_level(GPIO_PP1800_LID_EN_L, 1);
msleep(10);
gpio_set_level(GPIO_PP3300_USB_EN_L, 1);
msleep(10);
gpio_set_level(GPIO_PP3300_S0_EN_L, 1);
msleep(10);
gpio_set_level(GPIO_PP1800_S0_EN_L, 1);
msleep(10);
gpio_set_level(GPIO_AP_CORE_EN, 0);
/*
* Enable idle task deep sleep. Allow the low power idle task
@@ -267,12 +233,32 @@ enum power_state power_handle_state(enum power_state state)
/* Disable wireless */
wireless_set_state(WIRELESS_OFF);
gpio_set_level(GPIO_PP3300_TRACKPAD_EN_L, 1);
msleep(10);
gpio_set_level(GPIO_PP1800_SIXAXIS_EN_L, 1);
msleep(10);
gpio_set_level(GPIO_PP5000_EN, 0);
gpio_set_level(GPIO_LPDDR_PWR_EN, 0);
msleep(10);
gpio_set_level(GPIO_PP1800_AP_AVDD_EN_L, 1);
gpio_set_level(GPIO_PP1800_USB_EN_L, 1);
gpio_set_level(GPIO_PP1800_PMU_EN_L, 1);
msleep(10);
gpio_set_level(GPIO_PPVAR_CLOGIC_EN, 0);
msleep(10);
gpio_set_level(GPIO_PP900_PCIE_EN, 0);
gpio_set_level(GPIO_PP900_DDRPLL_EN, 0);
gpio_set_level(GPIO_PP900_USB_EN, 0);
gpio_set_level(GPIO_PP900_PLL_EN, 0);
gpio_set_level(GPIO_PP900_PMU_EN, 0);
msleep(10);
gpio_set_level(GPIO_PP900_AP_EN, 0);
gpio_set_level(GPIO_PPVAR_LOGIC_EN, 0);
/* Start shutting down */
return POWER_S5;
case POWER_S5G3:
/* Initialize power signal outputs to default. */
chipset_force_g3();
return POWER_G3;
}