usb pd:Correct the USB PD SinkWaitCap and PSHardReset timer values

Values should be as follows:
tTypeCSinkWaitCap: 310 to 620ms
tPSHardReset: 25 to 35ms
Current values are:
tTypeCSinkWaitCap (PD_T_SINK_WAIT_CAP): 240ms
tPSHardReset (PD_T_PS_HARD_RESET): 15ms

BUG=chromium:686122
TEST=manual testing on kevin along with make -j buildall
	- used a kevin to send a hard reset to uut
		> pd 0 hard
		C0 st36
		C0 st37
		34725 ms <-- time it took hard reset to execute
		C0 HARD RST TX

	- used a kevin, operating as source, that does not send
	  source caps to test a uut operating as a sink.
		C0 st6
		C0 st36
		613266 ms <-- time sink waited for source cap

	- plugged in charger and logged pd negotiation
		[1510.574091 event set 0x00200000]
		C0 st15
		C0 st3
		[1510.845115 event set 0x08000000]
		C0 st6
		Req C0 [1] 5000mV 3000mA
		[1510.945827 New chg p0]
		C0 st7
		[1510.949953 CL: pC0 st8
		0 s0 i500 v15000]
		[1510.954055 event set 0x00200000]
		[C0 st9
		1511.061285 event set 0x00400000]
		[1511.064752 CL: p0 s0 i3000 v5000]
		[Req C0 [3] 15000mV 3000mA
		1511.067538 event set 0x00200000]
		C0 st7
		C0 st8
		[1511.077896 CL: p0 s0 i500 v5000]
		[1511.079048 event set 0x00200000]
		C0 st9
		[1511.275448 CL: p0 s0 i3000 v15000]
		[1511.276913 event set 0x00200000]
		Req C0 [3] 15000mV 3000mA
		[1511.445719 CL: p0 s0 i500 v15000]
		[1511.446117 event set 0x00200000]
		C0 st7
		C0 st8
		C0 st9
		[1511.565730 CL: p0 s0 i3000 v15000]
		[1511.566566 event set 0x00200000]
		[1511.812205 event set 0x00400000]
		[1513.274941 event set 0x00200000]
		[1529.324670 Battery 90% / 0h:29 to full]
BRANCH=none

Change-Id: I6e80637cfc50dcfc431feb0e473ec22f408d6f1a
Reviewed-on: https://chromium-review.googlesource.com/434103
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Sam Hurst
2017-01-28 13:30:11 -08:00
committed by chrome-bot
parent a185dee8ca
commit 275cdfa556

View File

@@ -135,14 +135,14 @@ enum pd_rx_errors {
/* Timers */
#define PD_T_SEND_SOURCE_CAP (100*MSEC) /* between 100ms and 200ms */
#define PD_T_SINK_WAIT_CAP (240*MSEC) /* between 210ms and 250ms */
#define PD_T_SINK_WAIT_CAP (600*MSEC) /* between 310ms and 620ms */
#define PD_T_SINK_TRANSITION (35*MSEC) /* between 20ms and 35ms */
#define PD_T_SOURCE_ACTIVITY (45*MSEC) /* between 40ms and 50ms */
#define PD_T_SENDER_RESPONSE (30*MSEC) /* between 24ms and 30ms */
#define PD_T_PS_TRANSITION (500*MSEC) /* between 450ms and 550ms */
#define PD_T_PS_SOURCE_ON (480*MSEC) /* between 390ms and 480ms */
#define PD_T_PS_SOURCE_OFF (920*MSEC) /* between 750ms and 920ms */
#define PD_T_PS_HARD_RESET (15*MSEC) /* between 10ms and 20ms */
#define PD_T_PS_HARD_RESET (25*MSEC) /* between 25ms and 35ms */
#define PD_T_ERROR_RECOVERY (25*MSEC) /* 25ms */
#define PD_T_CC_DEBOUNCE (100*MSEC) /* between 100ms and 200ms */
/* DRP_SNK + DRP_SRC must be between 50ms and 100ms with 30%-70% duty cycle */