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cr50: enable AP and EC flash access

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The cr50 SPI master can control the external AP and EC SPI ROM. This
change adds support for doing spi_transactions, but does not use the SPI
transactions for anything except console commands. This support will be
used for flashing the AP and EC through CCD. For now AP and EC flash
select must be done manually using the spi_flash_select console command.
Flash select should be disabled after use, because it will prevent the
system from booting.

BUG=chrome-os-partner:50701
BRANCH=none
TEST=Enable spi_flash commands. Select AP ROM and verify spi_flashinfo,
read, erase, and write commands work properly. Select EC ROM and verify
the same commands.

Change-Id: I16c55015794f8513effe0fa5712488a84bed2627
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339844
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Mary Ruthven
2016-04-19 18:48:54 -07:00
committed by chrome-bot
parent 539e261d72
commit 2cab8b2081
4 changed files with 23 additions and 0 deletions
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7
board/cr50/board.c
View File

@@ -15,6 +15,7 @@
#include "usb_descriptor.h"
#include "usb_hid.h"
#include "util.h"
#include "spi.h"
/* Define interrupt and gpio structs */
#include "gpio_list.h"
@@ -123,6 +124,12 @@ const void * const usb_strings[] = {
BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
#endif
/* SPI devices */
const struct spi_device_t spi_devices[] = {
[CONFIG_SPI_FLASH_PORT] = {0, 4, GPIO_COUNT}
};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
int flash_regions_to_enable(struct g_flash_region *regions,
int max_regions)
{

6
board/cr50/board.h
View File

@@ -38,6 +38,12 @@
#define CONFIG_USB_PID 0x5014
/* Enable SPI Master (SPI) module */
#define CONFIG_SPI_MASTER
#define CONFIG_SPI_MASTER_NO_CS_GPIOS
#define CONFIG_SPI_MASTER_CONFIGURE_GPIOS
#define CONFIG_SPI_FLASH_PORT 0
/* Enable SPI Slave (SPS) module */
#define CONFIG_SPS
#define CONFIG_TPM_SPS

7
chip/g/spi_master.c
View File

@@ -211,6 +211,13 @@ static void spi_init(void)
{
size_t i;
#ifdef CONFIG_SPI_MASTER_CONFIGURE_GPIOS
/* Set SPI_MISO as an input */
GWRITE_FIELD(PINMUX, DIOA11_CTL, IE, 1); /* SPS_MISO */
/* Set SPI_CS to be an internal pull up */
GWRITE_FIELD(PINMUX, DIOA14_CTL, PU, 1);
#endif
for (i = 0; i < SPI_NUM_PORTS; i++) {
/* Configure the SPI ports to default to mode0. */
set_spi_clock_mode(i, SPI_CLOCK_MODE0);

3
include/config.h
View File

@@ -1606,6 +1606,9 @@
/* SPI master feature */
#undef CONFIG_SPI_MASTER
/* SPI master configure gpios on init */
#undef CONFIG_SPI_MASTER_CONFIGURE_GPIOS
/* Support SPI masters without GPIO-specified Chip Selects, instead rely on the
* SPI master port's hardwired CS pin. */
#undef CONFIG_SPI_MASTER_NO_CS_GPIOS