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rowan: fix SPI2 reset sequence and chip select ALT function

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EC controls SPI CS pin as GPIO. This CL remove the ALT function
config. And before trigger SPI hardware reset, the driver state needs to
be disable.

BUG=chrome-os-partner:62673
TEST=manual
  load into Rowan and boot up AP.
  check console command accelread
BRANCH=none

Change-Id: I511c5906efbbb42b09547c61414bcc24b0217ad3
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441485
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This commit is contained in:
Rong Chang
2017-02-11 11:34:59 +08:00
committed by chrome-bot
parent 9b2fe6349f
commit 2ed1cb0517
2 changed files with 2 additions and 1 deletions
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1
board/rowan/board.c
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@@ -430,6 +430,7 @@ static void board_chipset_pre_init(void)
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
spi_enable(CONFIG_SPI_ACCEL_PORT, 0);
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;

2
board/rowan/gpio.inc
View File

@@ -71,4 +71,4 @@ ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */
ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C MASTER:PB6/7 */
ALTERNATE(PIN_MASK(A, 0x1800), 5, MODULE_I2C, 0) /* I2C MASTER:PA11/12 */
ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI, 0) /* SPI SLAVE:PA4/5/6/7 */
ALTERNATE(PIN_MASK(B, 0xf000), 0, MODULE_SPI_MASTER, 0) /* SPI MASTER:PB12/13/14/15 */
ALTERNATE(PIN_MASK(B, 0xe000), 0, MODULE_SPI_MASTER, 0) /* SPI MASTER:PB13/14/15 */