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it8380dev: To config register 'GCR' in gpio_pre_init()

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The double-mapping modules(CIR, BRAM, SSPI, PECI, and UART) won't work
if GPD2 pin's status is low and GCR register's setting is at default.
We move 'IT83XX_GPIO_GCR = 0x06;' to 'gpio_pre_init()'
to prevent this case.

Signed-off-by: Dino Li <dino.li@ite.com.tw>

BRANCH=none
BUG=none
TEST=1. Register 'GCR'=0x6 after init.
     2. GPD2 is low and UART works.

Change-Id: I71b4436ab6c2a8f9e77e0d6f5116e5327a3167e7
Reviewed-on: https://chromium-review.googlesource.com/318131
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Dino Li
2015-12-14 17:10:44 +08:00
committed by chrome-bot
parent a6e82c3acd
commit 313f2ab8c5
2 changed files with 2 additions and 2 deletions
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2
chip/it83xx/gpio.c
View File

@@ -395,6 +395,8 @@ void gpio_pre_init(void)
int flags;
int i;
IT83XX_GPIO_GCR = 0x06;
for (i = 0; i < GPIO_COUNT; i++, g++) {
flags = g->flags;

2
chip/it83xx/lpc.c
View File

@@ -572,8 +572,6 @@ static void lpc_init(void)
*/
IT83XX_GCTRL_MCCR2 |= 0x10;
IT83XX_GPIO_GCR = 0x06;
/* The register pair to access PNPCFG is 004Eh and 004Fh */
IT83XX_GCTRL_BADRSEL = 0x01;