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Remove clock calibration for PIOSC

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Proto1 has A3 silicon which is factory-trimmed.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=chrome-os-partner:7693
TEST=boot and look for glitchy EC console.  If it's not glitchy, it worked.

Change-Id: I56cb2458e600e76e458bce0f24832ef4f456ac14
This commit is contained in:
Randall Spangler
2012-04-20 10:11:38 -07:00
parent 13ad1c007b
commit 34df8261f7
2 changed files with 16 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
chip/lm4/clock.c
View File

@@ -192,16 +192,11 @@ DECLARE_CONSOLE_COMMAND(nopll, command_disable_pll);
int clock_init(void)
{
#ifndef BOARD_bds
/* Only BDS has an external crystal; other boards don't have one, and
* can disable main oscillator control to reduce power consumption. */
LM4_SYSTEM_MOSCCTL = 0x04;
#endif
#ifdef BOARD_bds
/* Perform an auto calibration of the internal oscillator using the
* 32.768KHz hibernate clock, unless we've already done so. */
/* TODO: (crosbug.com/p/7693) This is only needed on early chips which
* aren't factory trimmed. */
* 32.768KHz hibernate clock, unless we've already done so. This is
* only necessary on A2 silicon as on BDS; A3 silicon is all
* factory-trimmed. */
if ((LM4_SYSTEM_PIOSCSTAT & 0x300) != 0x100) {
/* Start calibration */
LM4_SYSTEM_PIOSCCAL = 0x80000000;
@@ -211,6 +206,11 @@ int clock_init(void)
while (!(LM4_SYSTEM_PIOSCSTAT & 0x300))
;
}
#else
/* Only BDS has an external crystal; other boards don't have one, and
* can disable main oscillator control to reduce power consumption. */
LM4_SYSTEM_MOSCCTL = 0x04;
#endif
/* TODO: UART seems to glitch unless we wait 500k cycles before
* enabling the PLL, but only if this is a cold boot. Why? UART

8
chip/lm4/registers.h
View File

@@ -200,7 +200,13 @@ static inline int lm4_fan_addr(int ch, int offset)
#define LM4_SYSTEM_RCC_IOSCDIS (1 << 1)
#define LM4_SYSTEM_RCC_MOSCDIS (1 << 0)
#define LM4_SYSTEM_RCC2 LM4REG(0x400fe070)
#define LM4_SYSTEM_RCC2_USERCC2 (1 << 31)
#define LM4_SYSTEM_RCC2_USERCC2 (1 << 31)
#define LM4_SYSTEM_RCC2_DIV400 (1 << 30)
#define LM4_SYSTEM_RCC2_SYSDIV2(x) (((x) & 0x3f) << 23)
#define LM4_SYSTEM_RCC2_SYSDIV2LSB (1 << 22)
#define LM4_SYSTEM_RCC2_PWRDN2 (1 << 13)
#define LM4_SYSTEM_RCC2_BYPASS2 (1 << 11)
#define LM4_SYSTEM_RCC2_OSCSRC2(x) (((x) & 0x7) << 4)
#define LM4_SYSTEM_MOSCCTL LM4REG(0x400fe07c)
#define LM4_SYSTEM_PIOSCCAL LM4REG(0x400fe150)
#define LM4_SYSTEM_PIOSCSTAT LM4REG(0x400fe154)