UT for subsytem GPP

firmware/ec/src/subsystem/gpp/ebmp.c

@@ -234,12 +234,15 @@ static void ebmp_handle_irq(void *context) {
  *****************************************************************************/
 void ebmp_init(Gpp_gpioCfg *driver)
 {
-	pin_ap_boot_alert1 = &driver->pin_ap_boot_alert1;
-	pin_ap_boot_alert2 = &driver->pin_ap_boot_alert2;
-	pin_soc_pltrst_n = &driver->pin_soc_pltrst_n;
-	pin_soc_corepwr_ok = &driver->pin_soc_corepwr_ok;
+    pin_ap_boot_alert1 = &driver->pin_ap_boot_alert1;
+    pin_ap_boot_alert2 = &driver->pin_ap_boot_alert2;
+    pin_soc_pltrst_n = &driver->pin_soc_pltrst_n;
+    pin_soc_corepwr_ok = &driver->pin_soc_corepwr_ok;
 
-	if (pin_ap_boot_alert1->port) {
+    if (!driver) {
+        return;
+    }
+    if (pin_ap_boot_alert1->port) {
         const uint32_t pin_evt_cfg = OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_BOTH_EDGES;
         if (OcGpio_configure(pin_ap_boot_alert1, pin_evt_cfg) < OCGPIO_SUCCESS) {
             return RETURN_NOTOK;

firmware/ec/src/subsystem/gpp/gpp.c

@@ -33,6 +33,9 @@
 bool gpp_check_processor_reset(Gpp_gpioCfg *driver)
 {
     bool ret = false;
+    if (!driver) {
+        return ret;
+    }
     if (OcGpio_read(&driver->pin_soc_pltrst_n)) {
         ret = true;
     }
@@ -42,6 +45,9 @@ bool gpp_check_processor_reset(Gpp_gpioCfg *driver)
 bool gpp_check_core_power(Gpp_gpioCfg *driver)
 {
     bool ret = false;
+    if (!driver) {
+        return ret;
+    }
     if (OcGpio_read(&driver->pin_soc_corepwr_ok)) {
         ret = true;
     }
@@ -52,6 +58,9 @@ bool gpp_pmic_control(Gpp_gpioCfg *driver, uint8_t control)
 {
     bool ret = false;
 
+    if (!driver) {
+        return ret;
+    }
     if(control == OC_PMIC_ENABLE) {
         /*TODO:: Disabling for USB debugging*/
 
@@ -85,6 +94,9 @@ bool gpp_pmic_control(Gpp_gpioCfg *driver, uint8_t control)
 bool gpp_msata_das(Gpp_gpioCfg *driver)
 {
     bool ret = false;
+    if (!driver) {
+        return ret;
+    }
     if (!(OcGpio_read(&driver->pin_msata_ec_das))) {
         ret = true;
         LOGGER_DEBUG("GPP:INFO:: mSATA is active.\n");
@@ -95,6 +107,9 @@ bool gpp_msata_das(Gpp_gpioCfg *driver)
 bool gpp_pwrgd_protection(Gpp_gpioCfg *driver)
 {
     bool ret = false;
+    if (!driver) {
+        return ret;
+    }
     if (OcGpio_read(&driver->pin_lt4256_ec_pwrgd)) {
         ret = true;
     }
@@ -106,6 +121,9 @@ bool gpp_pwrgd_protection(Gpp_gpioCfg *driver)
  *****************************************************************************/
 bool gpp_pre_init(void* driver, void *returnValue)
 {
+    if(!driver) {
+        return false;
+    }
     Gpp_gpioCfg *gpioCfg = (Gpp_gpioCfg *)driver;
     OcGpio_configure(&gpioCfg->pin_soc_pltrst_n, OCGPIO_CFG_INPUT);
     OcGpio_configure(&gpioCfg->pin_soc_corepwr_ok, OCGPIO_CFG_INPUT);
@@ -124,6 +142,10 @@ bool gpp_pre_init(void* driver, void *returnValue)
 bool gpp_post_init(void* driver, void *ssState)
 {
     bool ret = false;
+
+    if(!(driver && ssState)) {
+        return ret;
+    }
     eSubSystemStates *newState = (eSubSystemStates*)ssState;
     if (!gpp_pwrgd_protection(driver)) {
         LOGGER_DEBUG("GPP:INFO:: LT4256 EC power good is for genration of 12V ok.\n");
@@ -151,6 +173,9 @@ bool gpp_post_init(void* driver, void *ssState)
  *****************************************************************************/
 static bool gpp_ap_reset(Gpp_gpioCfg *driver)
 {
+    if(!driver) {
+        return false;
+    }
     const OcGpio_Pin *pin = &(driver->pin_ec_reset_to_proc);
     if (OcGpio_write(pin, OC_GBC_PROC_RESET) < OCGPIO_SUCCESS) {
         return false;

firmware/ec/test/Makefile

@@ -146,6 +146,10 @@ TEST_OCGPIO_SRC=$(OCWARE_ROOT)/src/drivers/OcGpio.c $(OCWARE_ROOT)/src/devices/i
 $(PATHB)Test_OcGpio$(TARGET_EXTENSION): $(STD_FILES) $(TEST_OCGPIO_SRC)
 	$(C_COMPILER) $(CFLAGS) $(INC_DIRS) $(SYMBOLS) $^ -o $@    
 
+TEST_SUBSYS_GPP_SRC=$(OCWARE_ROOT)/src/subsystem/gpp/ebmp.c $(OCWARE_ROOT)/src/subsystem/gpp/gpp.c $(OCWARE_ROOT)/src/drivers/OcGpio.c fake/fake_GPIO.c fake/fake_ThreadedISR.c $(OCWARE_ROOT)/src/helpers/memory.c stub/stub_GateMutex.c stub/stub_Task.c stub/stub_Clock.c stub/stub_Semaphore.c $(OCWARE_ROOT)/platform/oc-sdr/cfg/OC_CONNECT_gbc.c
+$(PATHB)Test_subsys_gpp$(TARGET_EXTENSION): $(STD_FILES) $(TEST_SUBSYS_GPP_SRC)
+	$(C_COMPILER) $(CFLAGS) $(INC_DIRS) $(SYMBOLS) $^ -o $@    
+
 # Dummy target to allow us to force rebuild of testresults every time
 FORCE:
 

firmware/ec/test/inc/test_subsys_gpp.h

@@ -0,0 +1,23 @@
+/**
+* Copyright (c) 2017-present, Facebook, Inc.
+* All rights reserved.
+*
+* This source code is licensed under the BSD-style license found in the
+* LICENSE file in the root directory of this source tree. An additional grant
+* of patent rights can be found in the PATENTS file in the same directory.
+*/
+
+static OcGpio_Port ec_io = {
+    .fn_table = &FakeGpio_fnTable,
+    .object_data = &(FakeGpio_Obj){},
+};
+
+static bool gpp_GpioPins[] = {
+    [1] = 0x1, /* Pin = 1 */
+    [115] = 0x1,
+};
+
+static uint32_t gpp_GpioConfig[] = {
+    [1] = OCGPIO_CFG_INPUT,
+    [115] = OCGPIO_CFG_INPUT,
+};

firmware/ec/test/stub/stub_Clock.c

@@ -0,0 +1,18 @@
+/**
+ * Copyright (c) 2017-present, Facebook, Inc.
+ * All rights reserved.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree. An additional grant
+ * of patent rights can be found in the PATENTS file in the same directory.
+ */
+
+#include <ti/sysbios/knl/clock.h>
+#include "unity.h"
+
+xdc_Void ti_sysbios_knl_Clock_stop__E( ti_sysbios_knl_Clock_Handle __inst )
+{
+    TEST_ASSERT(__inst);
+    return;
+}
+

firmware/ec/test/stub/stub_Semaphore.c

@@ -0,0 +1,28 @@
+/**
+ * Copyright (c) 2017-present, Facebook, Inc.
+ * All rights reserved.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree. An additional grant
+ * of patent rights can be found in the PATENTS file in the same directory.
+ */
+
+#include <ti/sysbios/knl/Semaphore.h>
+#include "unity.h"
+
+xdc_Void ti_sysbios_knl_Semaphore_post__E( ti_sysbios_knl_Semaphore_Handle __inst )
+{
+    return;
+}
+
+ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_create( xdc_Int count,
+                                const ti_sysbios_knl_Semaphore_Params *__prms,
+                                xdc_runtime_Error_Block *__eb )
+{
+    return(ti_sysbios_knl_Semaphore_Handle)1;
+}
+
+xdc_Bool ti_sysbios_knl_Semaphore_pend__E( ti_sysbios_knl_Semaphore_Handle __inst, xdc_UInt32 timeout )
+{
+    return(1);
+}

firmware/ec/test/stub/stub_Task.c

@@ -0,0 +1,41 @@
+/**
+ * Copyright (c) 2017-present, Facebook, Inc.
+ * All rights reserved.
+ *
+ * This source code is licensed under the BSD-style license found in the
+ * LICENSE file in the root directory of this source tree. An additional grant
+ * of patent rights can be found in the PATENTS file in the same directory.
+ */
+
+#include <ti/sysbios/knl/Task.h>
+#include <stdbool.h>
+#include "unity.h"
+uint8_t taskCreated = false;
+uint8_t taskInit = false;
+
+void ti_sysbios_knl_Task_construct( ti_sysbios_knl_Task_Struct *__obj, ti_sysbios_knl_Task_FuncPtr fxn,
+                        const ti_sysbios_knl_Task_Params *__prms, xdc_runtime_Error_Block *__eb )
+{
+    TEST_ASSERT(__obj);
+    TEST_ASSERT(fxn);
+    TEST_ASSERT(__prms);
+    TEST_ASSERT_TRUE((__prms->stackSize > 0));
+    TEST_ASSERT_TRUE((__prms->priority > 0));
+    TEST_ASSERT_TRUE((__prms->stack));
+    TEST_ASSERT_TRUE(taskInit);
+
+    /* check for this in the test suite to indicate task is created */
+    taskCreated = true;
+
+    /* Reset */
+    taskInit = false;
+    return;
+}
+
+xdc_Void ti_sysbios_knl_Task_Params__init__S( xdc_Ptr dst, const xdc_Void *src, xdc_SizeT psz, xdc_SizeT isz )
+{
+    TEST_ASSERT(dst);
+    /* Init is done now task can be created */
+    taskInit = true;
+    return;
+}

firmware/ec/test/suites/Test_subsys_gpp.c

@@ -0,0 +1,257 @@
+#include "inc/subsystem/gpp/gpp.h"
+#include "inc/subsystem/gpp/ebmp.h"
+#include "fake/fake_GPIO.h"
+#include "fake/fake_I2C.h"
+#include <string.h>
+#include "unity.h"
+/* ======================== Constants & variables =========================== */
+uint8_t apUp = 1;
+extern uint8_t taskCreated;
+
+#define OC_PMIC_ENABLE          (1)
+#define OC_PMIC_DISABLE         (0)
+
+extern Gpp_gpioCfg gbc_gpp_gpioCfg;
+OcGpio_Port ec_io = {
+    .fn_table = &FakeGpio_fnTable,
+    .object_data = &(FakeGpio_Obj){},
+};
+
+static bool gpp_GpioPins[] = {
+    [1] = 0x1, /* Pin = 1 */
+    [115] = 0x1,
+};
+
+static uint32_t gpp_GpioConfig[] = {
+    [1] = OCGPIO_CFG_INPUT,
+    [115] = OCGPIO_CFG_INPUT,
+};
+
+extern int apState;
+
+/* ============================= Boilerplate ================================ */
+#include <ti/sysbios/knl/Task.h>
+unsigned int s_task_sleep_ticks;
+xdc_Void ti_sysbios_knl_Task_sleep__E( xdc_UInt32 nticks )
+{
+    s_task_sleep_ticks += nticks;
+}
+void SysCtlDelay(uint32_t ui32Count)
+{
+
+}
+
+void suite_setUp(void)
+{
+    FakeGpio_registerDevSimple(gpp_GpioPins, gpp_GpioConfig);
+}
+
+void setUp(void)
+{
+}
+
+void tearDown(void)
+{
+}
+
+void suite_tearDown(void)
+{
+}
+
+/* ================================ Tests =================================== */
+void test_gpp_check_processor_reset(void)
+{
+    gpp_GpioPins[57] = 1;
+    TEST_ASSERT_TRUE(gpp_check_processor_reset(&gbc_gpp_gpioCfg));
+    gpp_GpioPins[57] = 0;
+    TEST_ASSERT_FALSE(gpp_check_processor_reset(&gbc_gpp_gpioCfg));
+}
+
+void test_gpp_check_core_power(void)
+{
+    gpp_GpioPins[56] = 1;
+    TEST_ASSERT_TRUE(gpp_check_core_power(&gbc_gpp_gpioCfg));
+    gpp_GpioPins[56] = 0;
+    TEST_ASSERT_FALSE(gpp_check_core_power(&gbc_gpp_gpioCfg));
+}
+
+void test_gpp_pmic_control(void)
+{
+    /* ENABLE */
+    gpp_GpioPins[57] = 1;
+    gpp_GpioPins[56] = 1;
+    gpp_GpioPins[58] = 0;
+    TEST_ASSERT_TRUE(gpp_pmic_control(&gbc_gpp_gpioCfg, OC_PMIC_ENABLE));
+    TEST_ASSERT_EQUAL(OC_PMIC_ENABLE, gpp_GpioPins[58]);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[35], OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_BOTH_EDGES);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[83], OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_BOTH_EDGES);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[57], OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_BOTH_EDGES);
+
+    /* DISABLE */
+    gpp_GpioPins[58] = 1;
+    TEST_ASSERT_TRUE(gpp_pmic_control(&gbc_gpp_gpioCfg, OC_PMIC_DISABLE));
+    TEST_ASSERT_EQUAL(OC_PMIC_DISABLE, gpp_GpioPins[58]);
+
+    /* Invalid pin cases */
+    gpp_GpioPins[57] = 0;
+    gpp_GpioPins[56] = 1;
+    TEST_ASSERT_FALSE(gpp_pmic_control(&gbc_gpp_gpioCfg, OC_PMIC_ENABLE));
+
+    gpp_GpioPins[57] = 1;
+    gpp_GpioPins[56] = 0;
+    TEST_ASSERT_FALSE(gpp_pmic_control(&gbc_gpp_gpioCfg, OC_PMIC_ENABLE));
+
+    gpp_GpioPins[57] = 0;
+    gpp_GpioPins[56] = 0;
+    TEST_ASSERT_FALSE(gpp_pmic_control(&gbc_gpp_gpioCfg, OC_PMIC_ENABLE));
+
+    /* Invalid status cases */
+    gpp_GpioPins[57] = 1;
+    gpp_GpioPins[56] = 1;
+    TEST_ASSERT_FALSE(gpp_pmic_control(&gbc_gpp_gpioCfg, -1));
+    TEST_ASSERT_FALSE(gpp_pmic_control(&gbc_gpp_gpioCfg, 2));
+    TEST_ASSERT_FALSE(gpp_pmic_control(NULL, OC_PMIC_ENABLE));
+}
+
+void test_gpp_msata_das(void)
+{
+    gpp_GpioPins[113] = 0;
+    TEST_ASSERT_TRUE(gpp_msata_das(&gbc_gpp_gpioCfg));
+    gpp_GpioPins[113] = 1;
+    TEST_ASSERT_FALSE(gpp_msata_das(&gbc_gpp_gpioCfg));
+    TEST_ASSERT_FALSE(gpp_msata_das(NULL));
+}
+
+void test_gpp_pwrgd_protection(void)
+{
+    gpp_GpioPins[107] = 1;
+    TEST_ASSERT_TRUE(gpp_pwrgd_protection(&gbc_gpp_gpioCfg));
+    gpp_GpioPins[107] = 0;
+    TEST_ASSERT_FALSE(gpp_pwrgd_protection(&gbc_gpp_gpioCfg));
+    TEST_ASSERT_FALSE(gpp_pwrgd_protection(NULL));
+}
+
+void test_gpp_pre_init(void)
+{
+    gpp_GpioConfig[57] = 0;
+    gpp_GpioConfig[56] = 0;
+    gpp_GpioConfig[113] = 0;
+    gpp_GpioConfig[107] = 0;
+    gpp_GpioConfig[58] = 0;
+    gpp_GpioConfig[115] = 0;
+    
+    TEST_ASSERT_TRUE(gpp_pre_init(&gbc_gpp_gpioCfg, NULL));
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[57], OCGPIO_CFG_INPUT);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[56], OCGPIO_CFG_INPUT);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[113], OCGPIO_CFG_INPUT);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[107], OCGPIO_CFG_INPUT);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[58], OCGPIO_CFG_OUTPUT |
+                                             OCGPIO_CFG_OUT_LOW);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[115], OCGPIO_CFG_OUTPUT |
+                                                 OCGPIO_CFG_OUT_HIGH);
+}
+
+void test_gpp_post_init(void)
+{
+    eSubSystemStates state;
+    gpp_GpioPins[57] = 1;
+    gpp_GpioPins[56] = 1;
+    gpp_GpioPins[58] = 0;
+    gpp_GpioPins[107] = 0;
+    TEST_ASSERT_TRUE(gpp_post_init(&gbc_gpp_gpioCfg, &state));
+    TEST_ASSERT_EQUAL_HEX8(state, SS_STATE_CFG);
+
+    gpp_GpioPins[107] = 1;
+    TEST_ASSERT_FALSE(gpp_post_init(&gbc_gpp_gpioCfg, &state));
+    TEST_ASSERT_EQUAL_HEX8(state, SS_STATE_FAULTY);
+
+    gpp_GpioPins[107] = 0;
+    gpp_GpioPins[57] = 0;
+    gpp_GpioPins[56] = 1;
+    TEST_ASSERT_FALSE(gpp_post_init(&gbc_gpp_gpioCfg, &state));
+    TEST_ASSERT_EQUAL_HEX8(state, SS_STATE_FAULTY);
+    TEST_ASSERT_FALSE(gpp_post_init(NULL, &state));
+    TEST_ASSERT_FALSE(gpp_post_init(&gbc_gpp_gpioCfg, NULL));
+}
+
+void test_GPP_ap_Reset()
+{
+    gpp_GpioPins[115] = 0;
+
+    TEST_ASSERT_TRUE(GPP_ap_Reset(&gbc_gpp_gpioCfg, NULL));
+    TEST_ASSERT_EQUAL_HEX8(1, gpp_GpioPins[115]);
+    TEST_ASSERT_FALSE(GPP_ap_Reset(NULL, NULL));
+
+    //TODO: #489 GpioNative_write is successful for Input pins
+}
+
+void test_ebmp_create_task(void)
+{
+    /*
+     * Assertions checks are added in the create task RTOS system call 
+     */
+    taskCreated = false;
+    ebmp_create_task();
+    TEST_ASSERT_TRUE(taskCreated);
+}
+
+void test_ebmp_init(void)
+{
+    gpp_GpioConfig[35] = 0;
+    gpp_GpioConfig[83] = 0;
+    gpp_GpioConfig[57] = 0;
+
+    ebmp_init(&gbc_gpp_gpioCfg);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[35], OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_BOTH_EDGES);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[83], OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_BOTH_EDGES);
+    TEST_ASSERT_EQUAL_HEX8(gpp_GpioConfig[57], OCGPIO_CFG_INPUT | OCGPIO_CFG_INT_BOTH_EDGES);
+    ebmp_init(NULL);
+}
+
+void test_ebmp_check_stages(void)
+{
+    ebmp_init(&gbc_gpp_gpioCfg);
+    gpp_GpioPins[35] = 0;
+    gpp_GpioPins[83] = 0;
+    ebmp_check_boot_pin_status();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T1, apState);
+
+    gpp_GpioPins[35] = 1;
+    gpp_GpioPins[83] = 0;
+    ebmp_check_boot_pin_status();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T2, apState);
+    
+    gpp_GpioPins[35] = 1;
+    gpp_GpioPins[83] = 1;
+    ebmp_check_boot_pin_status();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T3, apState);
+
+    gpp_GpioPins[35] = 0;
+    gpp_GpioPins[83] = 1;
+    ebmp_check_boot_pin_status();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T4, apState);
+
+    gpp_GpioPins[35] = 0;
+    gpp_GpioPins[83] = 0;
+    ebmp_check_boot_pin_status();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T5, apState);
+
+    gpp_GpioPins[35] = 1;
+    gpp_GpioPins[83] = 0;
+    ebmp_check_boot_pin_status();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T6, apState);
+    
+    gpp_GpioPins[35] = 1;
+    gpp_GpioPins[83] = 1;
+    ebmp_check_boot_pin_status();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T7, apState);
+
+    gpp_GpioPins[57] = 1;
+    ebmp_check_soc_plt_reset();
+    TEST_ASSERT_EQUAL_HEX8(STATE_T0, apState);
+
+    gpp_GpioPins[56] = 0;
+    gpp_GpioPins[57] = 0;
+    ebmp_check_soc_plt_reset();
+    TEST_ASSERT_EQUAL_HEX8(STATE_INVALID, apState);
+}