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oak: using only one standby mode wakeup source.

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Before Oak rev4, it defines 2 wakeup source EC_WAKE(PA0), EC_PWR_BTN_L(PB5).
Due to the wakeup source limitation of STM32F0 (http://goo.gl/VQk9GV),
Oak can only use one wakeup source, because EC_PWR_BTN_L is low-active and
it is kept high always. The HW & SW should be changed after rev4:
Using PA0 as wakeup source only, instead of both (PA0 & PB5).

BRANCH=none
BUG=chrome-os-partner:46670
TEST=Manual on oak rev4 with HW rework.
Detach PD power adapter, run 'hibernate' on EC console, make sure that both
EC and PD go to hibernate, verify the following cases individually:
1. Press power button and verify that both EC and PD wake.
2. Plug PD power adapter and verfy that both EC and PD wake.

Change-Id: Ief37aa1f11a84dd358875f22fa35c484b10bc388
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/309246
Reviewed-by: Rong Chang <rongchang@chromium.org>
This commit is contained in:
Ben Lok
2015-10-28 10:43:49 +08:00
committed by chrome-bot
parent 2431602575
commit 37ff1d9696
1 changed files with 5 additions and 1 deletions
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6
board/oak/board.h
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@@ -46,7 +46,11 @@
* POWER_BUTTON_L: PB5 - WKUP6
*/
#define CONFIG_HIBERNATE
#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1|STM32_PWR_CSR_EWUP6)
#if BOARD_REV <= OAK_REV4
#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP6)
#else
#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1)
#endif /* BOARD_REV */
#define CONFIG_HOST_COMMAND_STATUS
#define CONFIG_HOSTCMD_PD
#define CONFIG_HOSTCMD_PD_PANIC