nds32: pre-fix for the latest official toolchain

We use the latest nde32 official toolchain to verify the bug of
GP-related instruction was fixed (we can remove "-mno-gp-direct" flag to
save code space), and code optimization.

We got some error on official toolchain, so we fix them as well:
- "break" instead of "trap".
  N8 CPU does not support "trap" instruction to generate an unconditional
  trap exception, but no error occurred while compiling by using current
  GCC toolchain (this will trigger a reserved instruction exception,
  so "ASSERT()" still work).
  We use "break" to generate a exception in this change.

- "li" instead of "la".
  To fix the error: "Error: la must use with symbol".

Also fix:
- The "_bss_start" has to be word-aligned because we use "lwi" instruction
  to load a word from the memory into the general register.

BRANCH=none
BUG=none
TEST=1. console command "crash assert".
     2. check registers settings: f02030h, f0203eh, and f02044h.

Change-Id: I33404a1d60eeebfa135bf43d3a7d5e73ab35c678
Reviewed-on: https://chromium-review.googlesource.com/422608
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

core/nds32/init.S

@@ -26,7 +26,7 @@ __entry_\()\name:
 	slt45 $r3, $sp /* if sp > end of system stack, then r15 = 1 and */
 	cmovn $sp, $r3, $r15 /* point sp to the top of the system stack */
 	/* save entry number of HW interrupt */
-	movi55  $r3, entry_number
+	movi55  $r3, \entry_number\()
 	swi.gp  $r3, [ + cpu_int_entry_number]
 	/* isr entry */
 	jal start_irq_handler
@@ -116,19 +116,19 @@ reset:
 	mtsr $r0, $mr7
 
 	/* Enable DLM 8k~12K(bit2) and DLM 12k~16k(bit3) */
-	la  $r1, 0x00F02030
+	li  $r1, 0x00F02030
 	lbi $r0, [$r1]
 	ori $r0, $r0, 0x0C
 	sbi $r0, [$r1]
 
 	/* Enable DLM 16k~36K bit[2-6] */
-	la  $r1, 0x00F0203E
+	li  $r1, 0x00F0203E
 	lbi $r0, [$r1]
 	ori $r0, $r0, 0x7C
 	sbi $r0, [$r1]
 
 	/* Enable DLM 36k~48K bit[0-2] */
-	la  $r1, 0x00F02044
+	li  $r1, 0x00F02044
 	lbi $r0, [$r1]
 	ori $r0, $r0, 0x7
 	sbi $r0, [$r1]
@@ -207,6 +207,7 @@ excep_handler:
 	/* we never return: exceptions are fatal */
 	j .
 
+.align 2
 _bss_start:
 .long __bss_start
 _bss_end:

core/nds32/panic.c

@@ -97,7 +97,7 @@ void software_panic(uint32_t reason, uint32_t info)
 	if (in_interrupt_context())
 		asm("j excep_handler");
 	else
-		asm("trap 0");
+		asm("break 0");
 }
 
 void panic_set_reason(uint32_t reason, uint32_t info, uint8_t exception)