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cleanup: Rename image geometry CONFIGs

Browse Source 
Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.

CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image

CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image

CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage

BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2015-05-11 10:16:41 -07:00
committed by ChromeOS Commit Bot
parent 3a36c29e67
commit 39bd18b890
36 changed files with 238 additions and 223 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Makefile
View File

@@ -93,10 +93,10 @@ ifneq "$(CONFIG_COMMON_RUNTIME)" "y"
endif
# Compute RW firmware size and offset
_rw_off_str:=$(shell echo "CONFIG_FW_RW_OFF" | $(CPP) $(CPPFLAGS) -P \
_rw_off_str:=$(shell echo "CONFIG_RW_MEM_OFF" | $(CPP) $(CPPFLAGS) -P \
-Ichip/$(CHIP) -Iboard/$(BOARD) -imacros include/config.h)
_rw_off:=$(shell echo "$$(($(_rw_off_str)))")
_rw_size_str:=$(shell echo "CONFIG_FW_RW_SIZE" | $(CPP) $(CPPFLAGS) -P \
_rw_size_str:=$(shell echo "CONFIG_RW_SIZE" | $(CPP) $(CPPFLAGS) -P \
-Ichip/$(CHIP) -Iboard/$(BOARD) -imacros include/config.h)
_rw_size:=$(shell echo "$$(($(_rw_size_str)))")
_flash_base_str:=$(shell echo "CONFIG_FLASH_BASE" | $(CPP) $(CPPFLAGS) -P \

6
board/zinger/board.c
View File

@@ -20,8 +20,8 @@
const struct rsa_public_key pkey __attribute__((section(".rsa_pubkey"))) =
#include "gen_pub_key.h"
/* The RSA signature is stored at the end of the RW firmware */
static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_FW_RW_OFF
+ CONFIG_FW_RW_SIZE - RSANUMBYTES;
static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF
+ CONFIG_RW_SIZE - RSANUMBYTES;
/* Large 768-Byte buffer for RSA computation : could be re-use afterwards... */
static uint32_t rsa_workbuf[3 * RSANUMWORDS];
@@ -29,7 +29,7 @@ extern void pd_rx_handler(void);
/* RW firmware reset vector */
static uint32_t * const rw_rst =
(uint32_t *)(CONFIG_FLASH_BASE+CONFIG_FW_RW_OFF+4);
(uint32_t *)(CONFIG_FLASH_BASE+CONFIG_RW_MEM_OFF+4);
/* External interrupt EXTINT7 for external comparator on PA7 */
void pd_rx_interrupt(void)

14
chip/g/config_std_flash.h
View File

@@ -7,7 +7,7 @@
#define __CROS_EC_CONFIG_STD_FLASH_H
/* RO firmware must start at beginning of flash */
#define CONFIG_FW_RO_OFF 0
#define CONFIG_RO_MEM_OFF 0
/*
* The EC uses the one bank of flash to emulate a SPI-like write protect
@@ -16,17 +16,17 @@
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
/* PSTATE immediately follows RO, in the first half of flash */
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
- CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE
#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE
#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
/* RW firmware is one firmware image offset from the start */
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_RO_SIZE
#endif /* __CROS_EC_CONFIG_STD_FLASH_H */

14
chip/host/config_chip.h
View File

@@ -26,18 +26,18 @@ extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE];
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put this after RO to give RW more space and make RO write protect region
* contiguous.
*/
#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE
#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
/* Maximum number of deferrable functions */

4
chip/host/system.c
View File

@@ -261,8 +261,8 @@ void system_pre_init(void)
system_set_reset_flags(load_reset_flags());
}
*(uintptr_t *)(__host_flash + CONFIG_FW_RO_OFF + 4) =
*(uintptr_t *)(__host_flash + CONFIG_RO_MEM_OFF + 4) =
(uintptr_t)__ro_jump_resetvec;
*(uintptr_t *)(__host_flash + CONFIG_FW_RW_OFF + 4) =
*(uintptr_t *)(__host_flash + CONFIG_RW_MEM_OFF + 4) =
(uintptr_t)__rw_jump_resetvec;
}

14
chip/it83xx/config_chip.h
View File

@@ -62,7 +62,7 @@
#endif
/* RO firmware must start at beginning of flash */
#define CONFIG_FW_RO_OFF 0
#define CONFIG_RO_MEM_OFF 0
/*
* The EC uses the one bank of flash to emulate a SPI-like write protect
@@ -71,18 +71,18 @@
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
/* PSTATE immediately follows RO, in the first half of flash */
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
- CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE
#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE
#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
/* RW firmware is one firmware image offset from the start */
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
/* TODO: why 2 sets of configs with the same numbers? */
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_RO_SIZE
/****************************************************************************/
/* Customize the build */

14
chip/lm4/config_chip.h
View File

@@ -75,7 +75,7 @@
#endif
/* RO firmware must start at beginning of flash */
#define CONFIG_FW_RO_OFF 0
#define CONFIG_RO_MEM_OFF 0
/*
* The EC uses the one bank of flash to emulate a SPI-like write protect
@@ -84,18 +84,18 @@
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
/* PSTATE immediately follows RO, in the first half of flash */
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE \
- CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE
#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE
#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
/* RW firmware is one firmware image offset from the start */
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_RO_SIZE
/****************************************************************************/
/* Lock the boot configuration to prevent brickage. */

20
chip/mec1322/config_chip.h
View File

@@ -110,20 +110,20 @@
#endif
/* RO/RW firmware must be after Loader code */
#define CONFIG_FW_RO_OFF CONFIG_FW_LOADER_SIZE
#define CONFIG_RO_MEM_OFF CONFIG_FW_LOADER_SIZE
#define CONFIG_FW_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
#define CONFIG_FW_INCLUDE_RO
#define CONFIG_FW_RW_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_RW_SIZE CONFIG_FW_RO_SIZE
#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
#define CONFIG_RW_SIZE CONFIG_RO_SIZE
/* Write protect Loader and RO Image */
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_LOADER_OFF
#define CONFIG_WP_OFF CONFIG_FW_LOADER_OFF
/* Write protect 128k section of 256k physical flash
which contains Loader and RO Images */
#define CONFIG_FW_WP_RO_SIZE (CONFIG_FLASH_PHYSICAL_SIZE >> 1)
#define CONFIG_WP_SIZE (CONFIG_FLASH_PHYSICAL_SIZE >> 1)
/****************************************************************************/
/* SPI Flash Memory Mapping */
@@ -132,12 +132,12 @@ which contains Loader and RO Images */
#define CONFIG_FLASH_BASE_SPI (CONFIG_SPI_FLASH_SIZE - (0x40000))
#define CONFIG_RO_WP_SPI_OFF 0x20000
#define CONFIG_RO_SPI_OFF 0x20000
#define CONFIG_RW_SPI_OFF 0
#define CONFIG_RO_STORAGE_OFF 0x20000
#define CONFIG_RW_STORAGE_OFF 0
#define CONFIG_RO_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \
CONFIG_RO_SPI_OFF)
CONFIG_RO_STORAGE_OFF)
#define CONFIG_RW_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \
CONFIG_RW_SPI_OFF)
CONFIG_RW_STORAGE_OFF)
/* Memory Lcation shared between lfw and RO/RWimage */
#define SHARED_RAM_LFW_RORW (CONFIG_MEC_SRAM_BASE_START + \
(CONFIG_LOADER_IMAGE_SIZE - 4))

14
chip/mec1322/flash.c
View File

@@ -123,8 +123,8 @@ int flash_physical_protect_now(int all)
offset = 0;
size = CONFIG_FLASH_PHYSICAL_SIZE;
} else {
offset = CONFIG_FW_RO_OFF;
size = CONFIG_FW_RO_SIZE;
offset = CONFIG_RO_MEM_OFF;
size = CONFIG_RO_SIZE;
}
spi_enable(1);
@@ -145,10 +145,10 @@ uint32_t flash_physical_get_protect_flags(void)
uint32_t flags = 0;
spi_enable(1);
if (spi_flash_check_protect(CONFIG_FW_RO_OFF, CONFIG_FW_RO_SIZE)) {
if (spi_flash_check_protect(CONFIG_RO_MEM_OFF, CONFIG_RO_SIZE)) {
flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
if (spi_flash_check_protect(CONFIG_FW_RW_OFF,
CONFIG_FW_RW_SIZE))
if (spi_flash_check_protect(CONFIG_RW_MEM_OFF,
CONFIG_RW_SIZE))
flags |= EC_FLASH_PROTECT_ALL_NOW;
}
spi_enable(0);
@@ -206,8 +206,8 @@ int flash_physical_protect_at_boot(enum flash_wp_range range)
offset = size = 0;
break;
case FLASH_WP_RO:
offset = CONFIG_FW_RO_OFF;
size = CONFIG_FW_RO_SIZE;
offset = CONFIG_RO_MEM_OFF;
size = CONFIG_RO_SIZE;
break;
case FLASH_WP_ALL:
offset = 0;

10
chip/mec1322/lfw/ec_lfw.c
View File

@@ -87,14 +87,14 @@ static int spi_flash_readloc(uint8_t *buf_usr,
int spi_rwimage_load(void)
{
uint8_t *buf = (uint8_t *) (CONFIG_FW_RW_OFF + CONFIG_FLASH_BASE);
uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE);
uint32_t i;
memset((void *)buf, 0xFF, (CONFIG_FW_RW_SIZE - 4));
memset((void *)buf, 0xFF, (CONFIG_RW_SIZE - 4));
spi_enable(1);
for (i = 0; i < CONFIG_FW_RW_SIZE; i += SPI_CHUNK_SIZE)
for (i = 0; i < CONFIG_RW_SIZE; i += SPI_CHUNK_SIZE)
spi_flash_readloc(&buf[i],
CONFIG_RW_IMAGE_FLASHADDR + i,
SPI_CHUNK_SIZE);
@@ -226,11 +226,11 @@ void lfw_main()
switch (*image_type) {
case SYSTEM_IMAGE_RW:
init_addr = CONFIG_FW_RW_OFF + CONFIG_FLASH_BASE;
init_addr = CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE;
spi_rwimage_load();
case SYSTEM_IMAGE_RO:
default:
init_addr = CONFIG_FW_RO_OFF + CONFIG_FLASH_BASE;
init_addr = CONFIG_RO_MEM_OFF + CONFIG_FLASH_BASE;
}
jump_to_image(*(uintptr_t *)(init_addr + 4));

2
chip/mec1322/system.c
View File

@@ -379,5 +379,5 @@ enum system_image_copy_t system_get_shrspi_image_copy(void)
/* TODO(crosbug.com/p/37510): Implement bootloader */
uint32_t system_get_lfw_address(uint32_t flash_addr)
{
return CONFIG_FW_RO_OFF;
return CONFIG_RO_MEM_OFF;
}

12
chip/npcx/config_chip.h
View File

@@ -75,17 +75,17 @@
#endif
/* RO firmware offset of flash */
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
/* RW firmware is one firmware image offset from the start */
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
/* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_RO_SIZE
/*
* The offset from top of flash wich used by booter

8
chip/npcx/lfw/ec_lfw.c
View File

@@ -83,12 +83,12 @@ bin2ram(void)
{
/* copy image from RO base */
if (IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION))
flash_burst_copy_fw_to_mram(CONFIG_FW_RO_OFF, CONFIG_CDRAM_BASE,
CONFIG_FW_RO_SIZE - LFW_SIZE);
flash_burst_copy_fw_to_mram(CONFIG_RO_MEM_OFF,
CONFIG_CDRAM_BASE, CONFIG_RO_SIZE - LFW_SIZE);
/* copy image from RW base */
else
flash_burst_copy_fw_to_mram(CONFIG_FW_RW_OFF, CONFIG_CDRAM_BASE,
CONFIG_FW_RW_SIZE - LFW_SIZE);
flash_burst_copy_fw_to_mram(CONFIG_RW_MEM_OFF,
CONFIG_CDRAM_BASE, CONFIG_RW_SIZE - LFW_SIZE);
/* Disable FIU pins to tri-state */
CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);

2
chip/npcx/system.c
View File

@@ -854,7 +854,7 @@ enum system_image_copy_t system_get_shrspi_image_copy(void)
static void system_sysjump(void)
{
/* Jump to RO region -- set flag */
if (base_addr == CONFIG_FLASH_BASE + CONFIG_FW_RO_OFF)
if (base_addr == CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF)
SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
else /* Jump to RW region -- clear flag */
CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);

12
chip/nrf51/config_chip.h
View File

@@ -48,17 +48,17 @@
#define CONFIG_FW_IMAGE_SIZE (128 * 1024)
/* Define the RO/RW offset */
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect
* region contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */

14
chip/stm32/config-stm32f03x.h
View File

@@ -20,12 +20,12 @@
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (16 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect region
@@ -37,7 +37,7 @@
#else
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#endif
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 32

14
chip/stm32/config-stm32f07x.h
View File

@@ -20,19 +20,19 @@
/* Size of the first firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_SIZE / 2)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_IMAGE_SIZE)
#define CONFIG_FW_RW_SIZE (CONFIG_FLASH_SIZE - CONFIG_FW_IMAGE_SIZE)
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF (CONFIG_RO_MEM_OFF + CONFIG_FW_IMAGE_SIZE)
#define CONFIG_RW_SIZE (CONFIG_FLASH_SIZE - CONFIG_FW_IMAGE_SIZE)
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect region
* contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 32

14
chip/stm32/config-stm32f100.h
View File

@@ -20,19 +20,19 @@
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect region
* contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 61

14
chip/stm32/config-stm32f10x.h
View File

@@ -20,19 +20,19 @@
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect region
* contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 68

14
chip/stm32/config-stm32f373.h
View File

@@ -20,19 +20,19 @@
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (128 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect region
* contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 81

14
chip/stm32/config-stm32l100.h
View File

@@ -29,19 +29,19 @@
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_RO_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect
* region contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 45

16
chip/stm32/config-stm32l15x.h
View File

@@ -29,19 +29,19 @@
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (64 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_RO_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect
* region contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 45

14
chip/stm32/config-stm32ts60.h
View File

@@ -20,19 +20,19 @@
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (32 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF
#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect region
* contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 59

8
common/firmware_image.lds.S
View File

@@ -14,17 +14,17 @@ MEMORY
SECTIONS
{
. = ALIGN(CONFIG_FLASH_BANK_SIZE);
.image.RO : AT(CONFIG_FLASH_BASE + CONFIG_FW_RO_OFF) {
.image.RO : AT(CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF) {
*(.image.RO)
} > FLASH =0xff
. = ALIGN(CONFIG_FLASH_BANK_SIZE);
#if (CONFIG_FW_RO_OFF == CONFIG_FW_RW_OFF)
#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
/* This is applicable to ECs in which RO and RW execution is
mapped to the same location but we still have to generate an ec.bin with RO
and RW images at different Flash offset */
.image.RW : AT(CONFIG_FLASH_BASE + CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) {
.image.RW : AT(CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) {
#else
.image.RW : AT(CONFIG_FLASH_BASE + CONFIG_FW_RW_OFF) {
.image.RW : AT(CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF) {
#endif
*(.image.RW)
} > FLASH =0xff

14
common/flash.c
View File

@@ -203,7 +203,7 @@ static const uintptr_t get_pstate_addr(void)
/* Always use the pstate data in RO, even if we're RW */
if (system_get_image_copy() == SYSTEM_IMAGE_RW)
addr += CONFIG_FW_RO_OFF - CONFIG_FW_RW_OFF;
addr += CONFIG_RO_MEM_OFF - CONFIG_RW_MEM_OFF;
return addr;
}
@@ -879,16 +879,16 @@ static int flash_command_region_info(struct host_cmd_handler_args *args)
switch (p->region) {
case EC_FLASH_REGION_RO:
r->offset = CONFIG_FW_RO_OFF;
r->size = CONFIG_FW_RO_SIZE;
r->offset = CONFIG_RO_MEM_OFF;
r->size = CONFIG_RO_SIZE;
break;
case EC_FLASH_REGION_RW:
r->offset = CONFIG_FW_RW_OFF;
r->size = CONFIG_FW_RW_SIZE;
r->offset = CONFIG_RW_MEM_OFF;
r->size = CONFIG_RW_SIZE;
break;
case EC_FLASH_REGION_WP_RO:
r->offset = CONFIG_FW_WP_RO_OFF;
r->size = CONFIG_FW_WP_RO_SIZE;
r->offset = CONFIG_WP_OFF;
r->size = CONFIG_WP_SIZE;
break;
default:
return EC_RES_INVALID_PARAM;

22
common/fmap.c
View File

@@ -69,15 +69,15 @@ const struct _ec_fmap {
* volatile data (ex, calibration results).
*/
.area_name = "EC_RO",
.area_offset = CONFIG_FW_RO_OFF,
.area_size = CONFIG_FW_RO_SIZE,
.area_offset = CONFIG_RO_MEM_OFF,
.area_size = CONFIG_RO_SIZE,
.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
},
{
/* (Optional) RO firmware code. */
.area_name = "FR_MAIN",
.area_offset = CONFIG_FW_RO_OFF,
.area_size = CONFIG_FW_RO_SIZE,
.area_offset = CONFIG_RO_MEM_OFF,
.area_size = CONFIG_RO_SIZE,
.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
},
{
@@ -86,7 +86,7 @@ const struct _ec_fmap {
* ASCII, and padded with \0.
*/
.area_name = "RO_FRID",
.area_offset = CONFIG_FW_RO_OFF +
.area_offset = CONFIG_RO_MEM_OFF +
RELATIVE((uint32_t)__version_struct_offset) +
offsetof(struct version_struct, version),
.area_size = sizeof(version_data.version),
@@ -96,7 +96,7 @@ const struct _ec_fmap {
/* Other RO stuff: FMAP, WP, KEYS, etc. */
{
.area_name = "FMAP",
.area_offset = CONFIG_FW_RO_OFF +
.area_offset = CONFIG_RO_MEM_OFF +
RELATIVE((uint32_t)&ec_fmap),
.area_size = sizeof(ec_fmap),
.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
@@ -108,8 +108,8 @@ const struct _ec_fmap {
* EC_RO and aligned to hardware specification.
*/
.area_name = "WP_RO",
.area_offset = CONFIG_FW_WP_RO_OFF,
.area_size = CONFIG_FW_WP_RO_SIZE,
.area_offset = CONFIG_WP_OFF,
.area_size = CONFIG_WP_SIZE,
.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
},
@@ -117,8 +117,8 @@ const struct _ec_fmap {
{
/* The range of RW firmware to be auto-updated. */
.area_name = "EC_RW",
.area_offset = CONFIG_FW_RW_OFF,
.area_size = CONFIG_FW_RW_SIZE,
.area_offset = CONFIG_RW_MEM_OFF,
.area_size = CONFIG_RW_SIZE,
.area_flags = FMAP_AREA_STATIC | FMAP_AREA_RO,
},
{
@@ -127,7 +127,7 @@ const struct _ec_fmap {
* ASCII, and padded with \0.
*/
.area_name = "RW_FWID",
.area_offset = CONFIG_FW_RW_OFF +
.area_offset = CONFIG_RW_MEM_OFF +
RELATIVE((uint32_t)__version_struct_offset) +
offsetof(struct version_struct, version),
.area_size = sizeof(version_data.version),

10
common/rwsig.c
View File

@@ -25,12 +25,12 @@ const struct rsa_public_key pkey __attribute__((section(".rsa_pubkey"))) =
#include "gen_pub_key.h"
/* The RSA signature is stored at the end of the RW firmware */
static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_FW_RW_OFF
+ CONFIG_FW_RW_SIZE - RSANUMBYTES;
static const void *rw_sig = (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF
+ CONFIG_RW_SIZE - RSANUMBYTES;
/* RW firmware reset vector */
static uint32_t * const rw_rst =
(uint32_t *)(CONFIG_FLASH_BASE+CONFIG_FW_RW_OFF+4);
(uint32_t *)(CONFIG_FLASH_BASE+CONFIG_RW_MEM_OFF+4);
void check_rw_signature(void)
{
@@ -58,8 +58,8 @@ void check_rw_signature(void)
/* SHA-256 Hash of the RW firmware */
SHA256_init(&ctx);
SHA256_update(&ctx, (void *)CONFIG_FLASH_BASE + CONFIG_FW_RW_OFF,
CONFIG_FW_RW_SIZE - RSANUMBYTES);
SHA256_update(&ctx, (void *)CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF,
CONFIG_RW_SIZE - RSANUMBYTES);
hash = SHA256_final(&ctx);
good = rsa_verify(&pkey, (void *)rw_sig, (void *)hash, rsa_workbuf);

24
common/system.c
View File

@@ -98,9 +98,9 @@ static uintptr_t get_base(enum system_image_copy_t copy)
{
switch (copy) {
case SYSTEM_IMAGE_RO:
return CONFIG_FLASH_BASE + CONFIG_FW_RO_OFF;
return CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF;
case SYSTEM_IMAGE_RW:
return CONFIG_FLASH_BASE + CONFIG_FW_RW_OFF;
return CONFIG_FLASH_BASE + CONFIG_RW_MEM_OFF;
default:
return 0xffffffff;
}
@@ -113,9 +113,9 @@ static uint32_t get_size(enum system_image_copy_t copy)
{
switch (copy) {
case SYSTEM_IMAGE_RO:
return CONFIG_FW_RO_SIZE;
return CONFIG_RO_SIZE;
case SYSTEM_IMAGE_RW:
return CONFIG_FW_RW_SIZE;
return CONFIG_RW_SIZE;
default:
return 0;
}
@@ -317,12 +317,12 @@ test_mockable enum system_image_copy_t system_get_image_copy(void)
uintptr_t my_addr = (uintptr_t)system_get_image_copy -
CONFIG_FLASH_BASE;
if (my_addr >= CONFIG_FW_RO_OFF &&
my_addr < (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE))
if (my_addr >= CONFIG_RO_MEM_OFF &&
my_addr < (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE))
return SYSTEM_IMAGE_RO;
if (my_addr >= CONFIG_FW_RW_OFF &&
my_addr < (CONFIG_FW_RW_OFF + CONFIG_FW_RW_SIZE))
if (my_addr >= CONFIG_RW_MEM_OFF &&
my_addr < (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE))
return SYSTEM_IMAGE_RW;
return SYSTEM_IMAGE_UNKNOWN;
@@ -357,12 +357,12 @@ test_mockable int system_unsafe_to_overwrite(uint32_t offset, uint32_t size)
switch (system_get_image_copy()) {
case SYSTEM_IMAGE_RO:
r_offset = CONFIG_FW_RO_OFF;
r_size = CONFIG_FW_RO_SIZE;
r_offset = CONFIG_RO_MEM_OFF;
r_size = CONFIG_RO_SIZE;
break;
case SYSTEM_IMAGE_RW:
r_offset = CONFIG_FW_RW_OFF;
r_size = CONFIG_FW_RW_SIZE;
r_offset = CONFIG_RW_MEM_OFF;
r_size = CONFIG_RW_SIZE;
break;
default:
return 0;

12
common/usb_pd_policy.c
View File

@@ -819,7 +819,7 @@ DECLARE_HOST_COMMAND(EC_CMD_USB_PD_GET_AMODE,
#endif
#define FW_RW_END (CONFIG_FW_RW_OFF + CONFIG_FW_RW_SIZE)
#define FW_RW_END (CONFIG_RW_MEM_OFF + CONFIG_RW_SIZE)
uint8_t *flash_hash_rw(void)
{
@@ -830,8 +830,8 @@ uint8_t *flash_hash_rw(void)
rw_flash_changed = 0;
SHA256_init(&ctx);
SHA256_update(&ctx, (void *)CONFIG_FLASH_BASE +
CONFIG_FW_RW_OFF,
CONFIG_FW_RW_SIZE - RSANUMBYTES);
CONFIG_RW_MEM_OFF,
CONFIG_RW_SIZE - RSANUMBYTES);
return SHA256_final(&ctx);
} else {
return ctx.buf;
@@ -881,14 +881,14 @@ int pd_custom_flash_vdm(int port, int cnt, uint32_t *payload)
if (system_get_image_copy() != SYSTEM_IMAGE_RO)
break;
pd_log_event(PD_EVENT_ACC_RW_ERASE, 0, 0, NULL);
flash_offset = CONFIG_FW_RW_OFF;
flash_physical_erase(CONFIG_FW_RW_OFF, CONFIG_FW_RW_SIZE);
flash_offset = CONFIG_RW_MEM_OFF;
flash_physical_erase(CONFIG_RW_MEM_OFF, CONFIG_RW_SIZE);
rw_flash_changed = 1;
break;
case VDO_CMD_FLASH_WRITE:
/* do not kill the code under our feet */
if ((system_get_image_copy() != SYSTEM_IMAGE_RO) ||
(flash_offset < CONFIG_FW_RW_OFF))
(flash_offset < CONFIG_RW_MEM_OFF))
break;
flash_physical_write(flash_offset, 4*(cnt - 1),
(const char *)(payload+1));

14
common/vboot_hash.c
View File

@@ -217,7 +217,7 @@ static void vboot_hash_init(void)
#endif
{
/* Start computing the hash of RW firmware */
vboot_hash_start(CONFIG_FW_RW_OFF,
vboot_hash_start(CONFIG_RW_MEM_OFF,
system_get_image_used(SYSTEM_IMAGE_RW),
NULL, 0);
}
@@ -251,8 +251,8 @@ DECLARE_HOOK(HOOK_SYSJUMP, vboot_hash_preserve_state, HOOK_PRIO_DEFAULT);
#ifdef CONFIG_CMD_HASH
static int command_hash(int argc, char **argv)
{
uint32_t offset = CONFIG_FW_RW_OFF;
uint32_t size = CONFIG_FW_RW_SIZE;
uint32_t offset = CONFIG_RW_MEM_OFF;
uint32_t size = CONFIG_RW_SIZE;
char *e;
if (argc == 1) {
@@ -277,12 +277,12 @@ static int command_hash(int argc, char **argv)
return EC_SUCCESS;
} else if (!strcasecmp(argv[1], "rw")) {
return vboot_hash_start(
CONFIG_FW_RW_OFF,
CONFIG_RW_MEM_OFF,
system_get_image_used(SYSTEM_IMAGE_RW),
NULL, 0);
} else if (!strcasecmp(argv[1], "ro")) {
return vboot_hash_start(
CONFIG_FW_RO_OFF,
CONFIG_RO_MEM_OFF,
system_get_image_used(SYSTEM_IMAGE_RO),
NULL, 0);
}
@@ -354,10 +354,10 @@ static int host_start_hash(const struct ec_params_vboot_hash *p)
/* Handle special offset values */
if (offset == EC_VBOOT_HASH_OFFSET_RO) {
offset = CONFIG_FW_RO_OFF;
offset = CONFIG_RO_MEM_OFF;
size = system_get_image_used(SYSTEM_IMAGE_RO);
} else if (p->offset == EC_VBOOT_HASH_OFFSET_RW) {
offset = CONFIG_FW_RW_OFF;
offset = CONFIG_RW_MEM_OFF;
size = system_get_image_used(SYSTEM_IMAGE_RW);
}

4
core/cortex-m/ec.lds.S
View File

@@ -5,10 +5,10 @@
#include "config.h"
#include "rsa.h"
#define FW_OFF_(section) CONFIG_FW_##section##_OFF
#define FW_OFF_(section) CONFIG_##section##_MEM_OFF
#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_OFF_(section))
#define FW_SIZE_(section) CONFIG_FW_##section##_SIZE
#define FW_SIZE_(section) CONFIG_##section##_SIZE
#define FW_SIZE(section) FW_SIZE_(section)

6
core/cortex-m/mpu.c
View File

@@ -140,14 +140,14 @@ int mpu_protect_ram(void)
int mpu_lock_ro_flash(void)
{
return mpu_lock_region(REGION_FLASH_MEMORY, CONFIG_FW_RO_OFF,
return mpu_lock_region(REGION_FLASH_MEMORY, CONFIG_RO_MEM_OFF,
CONFIG_FW_IMAGE_SIZE, MPU_ATTR_FLASH_MEMORY);
}
int mpu_lock_rw_flash(void)
{
return mpu_lock_region(REGION_FLASH_MEMORY, CONFIG_FW_RW_OFF,
CONFIG_FW_RW_SIZE, MPU_ATTR_FLASH_MEMORY);
return mpu_lock_region(REGION_FLASH_MEMORY, CONFIG_RW_MEM_OFF,
CONFIG_RW_SIZE, MPU_ATTR_FLASH_MEMORY);
}
int mpu_pre_init(void)

4
core/cortex-m0/ec.lds.S
View File

@@ -5,10 +5,10 @@
#include "config.h"
#include "rsa.h"
#define FW_OFF_(section) CONFIG_FW_##section##_OFF
#define FW_OFF_(section) CONFIG_##section##_MEM_OFF
#define FW_OFF(section) (CONFIG_FLASH_BASE + FW_OFF_(section))
#define FW_SIZE_(section) CONFIG_FW_##section##_SIZE
#define FW_SIZE_(section) CONFIG_##section##_SIZE
#define FW_SIZE(section) FW_SIZE_(section)

27
include/config.h
View File

@@ -644,12 +644,27 @@
#undef CONFIG_FW_IMAGE_SIZE
#undef CONFIG_FW_PSTATE_OFF
#undef CONFIG_FW_PSTATE_SIZE
#undef CONFIG_FW_RO_OFF
#undef CONFIG_FW_RO_SIZE
#undef CONFIG_FW_RW_OFF
#undef CONFIG_FW_RW_SIZE
#undef CONFIG_FW_WP_RO_OFF
#undef CONFIG_FW_WP_RO_SIZE
/*
* Read-only / read-write image configuration.
* Images may reside on storage (ex. external or internal SPI) at a different
* offset than when copied to program memory. Hence, two sets of offsets,
* for STORAGE and for MEMORY.
*/
#undef CONFIG_RO_MEM_OFF
#undef CONFIG_RO_STORAGE_OFF
#undef CONFIG_RO_SIZE
#undef CONFIG_RW_MEM_OFF
#undef CONFIG_RW_STORAGE_OFF
#undef CONFIG_RW_SIZE
/*
* Write protect region offset / size. This region normally encompasses the
* RO image, but may also contain additional images or data.
*/
#undef CONFIG_WP_OFF
#undef CONFIG_WP_SIZE
/*
* Board Image ec.bin contains a RO firmware. If not defined, the image will

8
include/flash.h
View File

@@ -15,12 +15,12 @@
#define PHYSICAL_BANKS (CONFIG_FLASH_PHYSICAL_SIZE / CONFIG_FLASH_BANK_SIZE)
/* Read-only firmware offset and size in units of flash banks */
#define RO_BANK_OFFSET (CONFIG_FW_RO_OFF / CONFIG_FLASH_BANK_SIZE)
#define RO_BANK_COUNT (CONFIG_FW_RO_SIZE / CONFIG_FLASH_BANK_SIZE)
#define RO_BANK_OFFSET (CONFIG_RO_MEM_OFF / CONFIG_FLASH_BANK_SIZE)
#define RO_BANK_COUNT (CONFIG_RO_SIZE / CONFIG_FLASH_BANK_SIZE)
/* Read-write firmware offset and size in units of flash banks */
#define RW_BANK_OFFSET (CONFIG_FW_RW_OFF / CONFIG_FLASH_BANK_SIZE)
#define RW_BANK_COUNT (CONFIG_FW_RW_SIZE / CONFIG_FLASH_BANK_SIZE)
#define RW_BANK_OFFSET (CONFIG_RW_MEM_OFF / CONFIG_FLASH_BANK_SIZE)
#define RW_BANK_COUNT (CONFIG_RW_SIZE / CONFIG_FLASH_BANK_SIZE)
/* Persistent protection state flash offset / size / bank */
#if defined(CONFIG_FLASH_PSTATE) && defined(CONFIG_FLASH_PSTATE_BANK)

44
test/flash.c
View File

@@ -286,11 +286,11 @@ static int test_overwrite_current(void)
/* Test that we cannot overwrite current image */
if (system_get_image_copy() == SYSTEM_IMAGE_RO) {
offset = CONFIG_FW_RO_OFF;
size = CONFIG_FW_RO_SIZE;
offset = CONFIG_RO_MEM_OFF;
size = CONFIG_RO_SIZE;
} else {
offset = CONFIG_FW_RW_OFF;
size = CONFIG_FW_RW_SIZE;
offset = CONFIG_RW_MEM_OFF;
size = CONFIG_RW_SIZE;
}
#ifdef EMU_BUILD
@@ -312,11 +312,11 @@ static int test_overwrite_other(void)
/* Test that we can overwrite the other image */
if (system_get_image_copy() == SYSTEM_IMAGE_RW) {
offset = CONFIG_FW_RO_OFF;
size = CONFIG_FW_RO_SIZE;
offset = CONFIG_RO_MEM_OFF;
size = CONFIG_RO_SIZE;
} else {
offset = CONFIG_FW_RW_OFF;
size = CONFIG_FW_RW_SIZE;
offset = CONFIG_RW_MEM_OFF;
size = CONFIG_RW_SIZE;
}
#ifdef EMU_BUILD
@@ -335,10 +335,10 @@ static int test_overwrite_other(void)
static int test_op_failure(void)
{
mock_flash_op_fail = EC_ERROR_UNKNOWN;
VERIFY_NO_WRITE(CONFIG_FW_RO_OFF, sizeof(testdata), testdata);
VERIFY_NO_WRITE(CONFIG_FW_RW_OFF, sizeof(testdata), testdata);
VERIFY_NO_ERASE(CONFIG_FW_RO_OFF, CONFIG_FLASH_ERASE_SIZE);
VERIFY_NO_ERASE(CONFIG_FW_RW_OFF, CONFIG_FLASH_ERASE_SIZE);
VERIFY_NO_WRITE(CONFIG_RO_MEM_OFF, sizeof(testdata), testdata);
VERIFY_NO_WRITE(CONFIG_RW_MEM_OFF, sizeof(testdata), testdata);
VERIFY_NO_ERASE(CONFIG_RO_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
VERIFY_NO_ERASE(CONFIG_RW_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
mock_flash_op_fail = EC_SUCCESS;
return EC_SUCCESS;
@@ -360,11 +360,11 @@ static int test_flash_info(void)
static int test_region_info(void)
{
VERIFY_REGION_INFO(EC_FLASH_REGION_RO,
CONFIG_FW_RO_OFF, CONFIG_FW_RO_SIZE);
CONFIG_RO_MEM_OFF, CONFIG_RO_SIZE);
VERIFY_REGION_INFO(EC_FLASH_REGION_RW,
CONFIG_FW_RW_OFF, CONFIG_FW_RW_SIZE);
CONFIG_RW_MEM_OFF, CONFIG_RW_SIZE);
VERIFY_REGION_INFO(EC_FLASH_REGION_WP_RO,
CONFIG_FW_WP_RO_OFF, CONFIG_FW_WP_RO_SIZE);
CONFIG_WP_OFF, CONFIG_WP_SIZE);
return EC_SUCCESS;
}
@@ -391,16 +391,16 @@ static int test_write_protect(void)
ASSERT_WP_FLAGS(EC_FLASH_PROTECT_ALL_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
/* Check we cannot erase anything */
TEST_ASSERT(flash_physical_erase(CONFIG_FW_RO_OFF,
TEST_ASSERT(flash_physical_erase(CONFIG_RO_MEM_OFF,
CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
TEST_ASSERT(flash_physical_erase(CONFIG_FW_RW_OFF,
TEST_ASSERT(flash_physical_erase(CONFIG_RW_MEM_OFF,
CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
/* We should not even try to write/erase */
VERIFY_NO_ERASE(CONFIG_FW_RO_OFF, CONFIG_FLASH_ERASE_SIZE);
VERIFY_NO_ERASE(CONFIG_FW_RW_OFF, CONFIG_FLASH_ERASE_SIZE);
VERIFY_NO_WRITE(CONFIG_FW_RO_OFF, sizeof(testdata), testdata);
VERIFY_NO_WRITE(CONFIG_FW_RW_OFF, sizeof(testdata), testdata);
VERIFY_NO_ERASE(CONFIG_RO_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
VERIFY_NO_ERASE(CONFIG_RW_MEM_OFF, CONFIG_FLASH_ERASE_SIZE);
VERIFY_NO_WRITE(CONFIG_RO_MEM_OFF, sizeof(testdata), testdata);
VERIFY_NO_WRITE(CONFIG_RW_MEM_OFF, sizeof(testdata), testdata);
return EC_SUCCESS;
}
@@ -409,7 +409,7 @@ static int test_boot_write_protect(void)
{
/* Check write protect state persists through reboot */
ASSERT_WP_FLAGS(EC_FLASH_PROTECT_RO_NOW | EC_FLASH_PROTECT_RO_AT_BOOT);
TEST_ASSERT(flash_physical_erase(CONFIG_FW_RO_OFF,
TEST_ASSERT(flash_physical_erase(CONFIG_RO_MEM_OFF,
CONFIG_FLASH_ERASE_SIZE) != EC_SUCCESS);
return EC_SUCCESS;