mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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Intel GLK-RVP: Add initial board bringup code
Added bare minimum code to bringup the Intel GLK-RVP using Nuvoton AIC. BUG=b:64394037 BRANCH=glkrvp TEST=Intel GLK-RVP2.0 boots to Chrome OS using Nuvoton AIC. Change-Id: I86816d09fe428091438a16f014e23b2e0c0025b7 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/602515 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This commit is contained in:
Vijay Hiremath
committed by
chrome-bot
chrome-bot
parent
5f72f0a085
commit
3bd19634bb
124
board/glkrvp/board.c
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124
board/glkrvp/board.c
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@@ -0,0 +1,124 @@
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Intel GLK-RVP board-specific configuration */
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#include "chipset.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "host_command.h"
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#include "i2c.h"
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#include "keyboard_scan.h"
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#include "lid_switch.h"
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#include "power.h"
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#include "power_button.h"
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#include "spi.h"
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#include "switch.h"
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#include "system.h"
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#include "task.h"
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#include "timer.h"
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#include "uart.h"
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#include "util.h"
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#include "gpio_list.h"
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/* power signal list. Must match order of enum power_signal. */
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const struct power_signal_info power_signal_list[] = {
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{GPIO_RSMRST_L_PGOOD, 1, "RSMRST_L"},
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{GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"},
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{GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"},
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{GPIO_ALL_SYS_PGOOD, 1, "ALL_SYS_PGOOD"},
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};
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BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
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/* I2C ports */
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const struct i2c_port_t i2c_ports[] = {
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{"master0-0", NPCX_I2C_PORT0_0, 400, GPIO_I2C0_SCL0, GPIO_I2C0_SDA0},
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{"master0-1", NPCX_I2C_PORT0_1, 400, GPIO_I2C0_SCL1, GPIO_I2C0_SDA1},
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{"master1", NPCX_I2C_PORT1, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
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{"master2", NPCX_I2C_PORT2, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
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{"master3", NPCX_I2C_PORT3, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
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};
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const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
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/* Wake-up pins for hibernate */
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const enum gpio_signal hibernate_wake_pins[] = {
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GPIO_POWER_BUTTON_L,
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};
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const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
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/* Called by APL power state machine when transitioning from G3 to S5 */
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static void chipset_pre_init(void)
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{
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/*
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* No need to re-init PMIC since settings are sticky across sysjump.
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* However, be sure to check that PMIC is already enabled. If it is
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* then there's no need to re-sequence the PMIC.
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*/
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if (system_jumped_to_this_image())
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return;
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/* TODO: Enable PMIC */
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}
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DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, chipset_pre_init, HOOK_PRIO_DEFAULT);
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/* Initialize board. */
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static void board_init(void)
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{
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}
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DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_FIRST);
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/* Called on AP S5 -> S3 transition */
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static void board_chipset_startup(void)
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{
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}
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DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT);
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/* Called on AP S3 -> S5 transition */
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static void board_chipset_shutdown(void)
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{
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}
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DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);
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void chipset_do_shutdown(void)
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{
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/* TODO: Disable PMIC */
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/* gpio_set_level(GPIO_PMIC_EN, 0); */
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}
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void board_hibernate_late(void)
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{
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}
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void board_hibernate(void)
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{
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/*
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* To support hibernate called from console commands, ectool commands
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* and key sequence, shutdown the AP before hibernating.
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*/
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chipset_do_shutdown();
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/* Added delay to allow AP to settle down */
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msleep(100);
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}
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int charge_prevent_power_on(int power_button_pressed)
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{
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return 0;
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}
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int extpower_is_present(void)
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{
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return 1;
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}
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int charge_want_shutdown(void)
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{
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return 0;
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}
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102
board/glkrvp/board.h
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102
board/glkrvp/board.h
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@@ -0,0 +1,102 @@
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Intel GLK-RVP board-specific configuration */
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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/*
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* Allow dangerous commands.
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* TODO: Remove this config before production.
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*/
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#define CONFIG_SYSTEM_UNLOCKED
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#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
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#undef CONFIG_HOSTCMD_DEBUG_MODE
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/*
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* By default, enable all console messages excepted HC, ACPI and event:
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* The sensor stack is generating a lot of activity.
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*/
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#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
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/* EC console commands */
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/* Battery */
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/* Charger */
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/* Keyboard */
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#define CONFIG_KEYBOARD_PROTOCOL_8042
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/* UART */
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#define NPCX_UART_MODULE2 1 /* 0:GPIO10/11 1:GPIO64/65 as UART */
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/* USB-A config */
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/* USB PD config */
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/* SoC / PCH */
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#define CONFIG_LPC
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#define CONFIG_CHIPSET_APOLLOLAKE
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#define CONFIG_CHIPSET_RESET_HOOK
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#define CONFIG_POWER_BUTTON
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#define CONFIG_POWER_BUTTON_X86
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#define CONFIG_POWER_COMMON
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/* EC */
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#define CONFIG_WP_ALWAYS
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#define CONFIG_I2C
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#define CONFIG_I2C_MASTER
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#define CONFIG_LID_SWITCH
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#define CONFIG_LTO
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#define CONFIG_UART_HOST 0
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#define CONFIG_FLASH_SIZE 524288
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#define CONFIG_SPI_FLASH_REGS
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#define CONFIG_SPI_FLASH_W25Q40
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/*
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* Enable 1 slot of secure temporary storage to support
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* suspend/resume with read/write memory training.
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*/
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#define CONFIG_VSTORE
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#define CONFIG_VSTORE_SLOT_COUNT 1
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/* Optional feature - used by nuvoton */
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#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 1:GPIOD5/E2/D4/E5 as JTAG*/
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#define NPCX_TACH_SEL2 0 /* 0:GPIO40/A4 1:GPIO93/D3 as TACH */
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/* I2C ports */
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/* EC exclude modules */
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#undef CONFIG_ADC
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#undef CONFIG_PECI
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#undef CONFIG_SWITCH
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#undef CONFIG_WATCHDOG
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#ifndef __ASSEMBLER__
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#include "gpio_signal.h"
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#include "registers.h"
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enum power_signal {
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X86_RSMRST_N = 0,
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X86_SLP_S3_N,
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X86_SLP_S4_N,
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X86_ALL_SYS_PG, /* PMIC_EC_PWROK_OD */
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/* Number of X86 signals */
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POWER_SIGNAL_COUNT
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};
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/* Define typical operating power and max power */
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#endif /* !__ASSEMBLER__ */
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#endif /* __CROS_EC_BOARD_H */
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12
board/glkrvp/build.mk
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12
board/glkrvp/build.mk
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@@ -0,0 +1,12 @@
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# -*- makefile -*-
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# Copyright 2017 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# Board specific files build
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#
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CHIP:=npcx
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CHIP_VARIANT:=npcx5m6g
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board-y=board.o
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33
board/glkrvp/ec.tasklist
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33
board/glkrvp/ec.tasklist
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/*
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* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Intel RVP board-specific configuration */
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/*
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* List of enabled tasks in the priority order
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*
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* The first one has the lowest priority.
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*
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* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
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* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
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* where :
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* 'n' in the name of the task
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* 'r' in the main routine of the task
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* 'd' in an opaque parameter passed to the routine at startup
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* 's' is the stack size in bytes; must be a multiple of 8
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*
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* For USB PD tasks, IDs must be in consecutive order and correspond to
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* the port which they are for. See TASK_ID_TO_PD_PORT() macro.
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*/
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#define CONFIG_TASK_LIST \
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TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
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TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
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TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
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161
board/glkrvp/gpio.inc
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161
board/glkrvp/gpio.inc
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@@ -0,0 +1,161 @@
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/* -*- mode:c -*-
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*
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* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Intel GLK-RVP board-specific configuration */
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/*
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* Declare symbolic names for all the GPIOs that we care about.
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* Note: Those with interrupt handlers must be declared first.
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*/
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GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */
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GPIO_INT(PCH_SLP_S3_L, PIN(8, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */
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GPIO_INT(RSMRST_L_PGOOD, PIN(3, 6), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */
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GPIO_INT(ALL_SYS_PGOOD, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_ODL */
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GPIO_INT(POWER_BUTTON_L, PIN(A, 6), GPIO_INT_BOTH, power_button_interrupt) /* MECH_PWR_BTN_ODL */
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GPIO_INT(LID_OPEN, PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt) /* SMC_LID */
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GPIO(PCH_SMI_L, PIN(C, 6), GPIO_ODR_HIGH) /* EC_SMI_ODL */
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GPIO(PCH_SCI_L, PIN(7, 6), GPIO_ODR_HIGH) /* EC_SCI_ODL */
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GPIO(PCH_PWRBTN_L, PIN(7, 5), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */
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GPIO(PCH_WAKE_L, PIN(7, 0), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */
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GPIO(PCH_SYS_PWROK, PIN(3, 5), GPIO_OUT_LOW) /* EC_PCH_PWROK */
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GPIO(ENABLE_BACKLIGHT, PIN(9, 7), GPIO_ODR_HIGH) /* EC_BL_EN_OD */
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GPIO(ENTERING_RW, PIN(A, 7), GPIO_OUTPUT) /* EC_ENTERING_RW */
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GPIO(PCH_RSMRST_L, PIN(0, 1), GPIO_OUT_LOW) /* EC_PCH_RSMRST_L */
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GPIO(PCH_RCIN_L, PIN(0, 0), GPIO_ODR_HIGH) /* SYS_RST_ODL */
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GPIO(PCH_SLP_S0_L, PIN(8, 1), GPIO_INPUT) /* SLP_S0_L */
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GPIO(SMC_SHUTDOWN, PIN(3, 3), GPIO_OUT_LOW | GPIO_PULL_DOWN) /* A_RAIL_EN */
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/*
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* PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is
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* normally driven by the PMIC. The EC can also drive this signal in the event
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* that the ambient or charger temperature sensors exceeds their thresholds.
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*/
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GPIO(CPU_PROCHOT, PIN(A, 3), GPIO_INPUT) /* PCH_PROCHOT_ODL */
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GPIO(EC_PCH_RTCRST, PIN(B, 7), GPIO_INPUT) /* EC_PCH_RTCRST TODO: Not used yet */
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/*
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* I2C pins should be configured as inputs until I2C module is
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* initialized. This will avoid driving the lines unintentionally.
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*/
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GPIO(I2C0_SCL0, PIN(B, 5), GPIO_ODR_HIGH)
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GPIO(I2C0_SDA0, PIN(B, 4), GPIO_ODR_HIGH)
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GPIO(I2C0_SCL1, PIN(B, 3), GPIO_ODR_HIGH)
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GPIO(I2C0_SDA1, PIN(B, 2), GPIO_ODR_HIGH)
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GPIO(I2C1_SCL, PIN(9, 0), GPIO_ODR_HIGH)
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GPIO(I2C1_SDA, PIN(8, 7), GPIO_ODR_HIGH)
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GPIO(I2C2_SCL, PIN(9, 2), GPIO_ODR_HIGH)
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GPIO(I2C2_SDA, PIN(9, 1), GPIO_ODR_HIGH)
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GPIO(I2C3_SCL, PIN(D, 1), GPIO_ODR_HIGH)
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GPIO(I2C3_SDA, PIN(D, 0), GPIO_ODR_HIGH)
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/* Unused pins 3.3V & Interruptable */
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GPIO(NC_02, PIN(0, 2), GPIO_INPUT)
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GPIO(NC_04, PIN(0, 4), GPIO_INPUT)
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GPIO(NC_34, PIN(3, 4), GPIO_INPUT)
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GPIO(NC_37, PIN(3, 7), GPIO_INPUT)
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GPIO(NC_41, PIN(4, 1), GPIO_INPUT)
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GPIO(NC_42, PIN(4, 2), GPIO_INPUT)
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GPIO(NC_60, PIN(6, 0), GPIO_INPUT)
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GPIO(NC_62, PIN(6, 2), GPIO_INPUT)
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GPIO(NC_63, PIN(6, 3), GPIO_INPUT)
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GPIO(NC_71, PIN(7, 1), GPIO_INPUT)
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GPIO(NC_73, PIN(7, 3), GPIO_INPUT)
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GPIO(NC_74, PIN(7, 4), GPIO_INPUT)
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GPIO(NC_80, PIN(8, 0), GPIO_INPUT)
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GPIO(NC_82, PIN(8, 2), GPIO_INPUT)
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GPIO(NC_83, PIN(8, 3), GPIO_INPUT)
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GPIO(NC_84, PIN(8, 4), GPIO_INPUT)
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GPIO(NC_B1, PIN(B, 1), GPIO_INPUT)
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GPIO(NC_C0, PIN(C, 0), GPIO_INPUT)
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GPIO(NC_C1, PIN(C, 1), GPIO_INPUT)
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GPIO(NC_C2, PIN(C, 2), GPIO_INPUT)
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GPIO(NC_C3, PIN(C, 3), GPIO_INPUT)
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GPIO(NC_C4, PIN(C, 4), GPIO_INPUT)
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GPIO(NC_C5, PIN(C, 5), GPIO_INPUT)
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GPIO(NC_C7, PIN(C, 7), GPIO_INPUT)
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GPIO(NC_D2, PIN(D, 2), GPIO_INPUT)
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GPIO(NC_D3, PIN(D, 3), GPIO_INPUT)
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GPIO(NC_E7, PIN(E, 7), GPIO_INPUT)
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/* Unused pins: VSPI 3.3V or 1.8V & Interruptable */
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GPIO(NC_93, PIN(9, 3), GPIO_INPUT)
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GPIO(NC_94, PIN(9, 4), GPIO_INPUT)
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GPIO(NC_95, PIN(9, 5), GPIO_INPUT)
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GPIO(NC_A1, PIN(A, 1), GPIO_INPUT)
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GPIO(NC_A5, PIN(A, 5), GPIO_INPUT)
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GPIO(NC_B0, PIN(B, 0), GPIO_INPUT)
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/* Unused pins 3.3V & Non-Interruptable */
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GPIO(NC_32, PIN(3, 2), GPIO_INPUT)
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GPIO(NC_66, PIN(6, 6), GPIO_INPUT)
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GPIO(NC_B6, PIN(B, 6), GPIO_INPUT)
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/* eSPI: VHIF Unused pins 1.8V & Interruptable */
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GPIO(NC_46, PIN(4, 6), GPIO_INPUT)
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GPIO(NC_47, PIN(4, 7), GPIO_INPUT)
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GPIO(NC_50, PIN(5, 0), GPIO_INPUT)
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GPIO(NC_51, PIN(5, 1), GPIO_INPUT)
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GPIO(NC_52, PIN(5, 2), GPIO_INPUT)
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GPIO(NC_53, PIN(5, 3), GPIO_INPUT)
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GPIO(NC_54, PIN(5, 4), GPIO_INPUT)
|
||||
GPIO(NC_55, PIN(5, 5), GPIO_INPUT)
|
||||
GPIO(NC_56, PIN(5, 6), GPIO_INPUT)
|
||||
GPIO(NC_57, PIN(5, 7), GPIO_INPUT)
|
||||
|
||||
/* Alternate pins for UART */
|
||||
ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* GPIO64/65 */
|
||||
|
||||
/* Alternate pins for I2C */
|
||||
ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* I2C0SDA1/I2C0SCL1 GPIOB2/B3 */
|
||||
ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* I2C0SDA0/I2C0SCL0 GPIOB4/B5 */
|
||||
ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* I2C1SDA GPIO87 */
|
||||
ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0) /* I2C1SCL/I2C2SDA/I2C2SCL GPIO90/91/92 */
|
||||
ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA/I2C3SCL GPIOD0/D1 */
|
||||
|
||||
/* Alternate pins for ADC/SPI/PWM/MFT */
|
||||
ALTERNATE(PIN_MASK(4, 0x38), 1, MODULE_ADC, 0) /* ADC GPIO45/44/43 */
|
||||
ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
|
||||
ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO GPIO95 */
|
||||
ALTERNATE(PIN_MASK(C, 0x04), 3, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */
|
||||
/* Alternative functionality for FANS */
|
||||
#ifdef CONFIG_FANS
|
||||
ALTERNATE(PIN_MASK(C, 0x08), 7, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */
|
||||
#if NPCX_TACH_SEL2
|
||||
ALTERNATE(PIN_MASK(9, 0x08), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */
|
||||
#else
|
||||
ALTERNATE(PIN_MASK(4, 0x01), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Keyboard pins */
|
||||
#define GPIO_KB_INPUT (GPIO_INPUT)
|
||||
#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
|
||||
|
||||
/* Keyboard Columns */
|
||||
ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) /* GPIO05/06/07 */
|
||||
ALTERNATE(PIN_MASK(1, 0xFF), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) /* GPIO10/11/12/13/14/15/16/17 */
|
||||
ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT) /* GPIO20/21 */
|
||||
|
||||
/* Keyboard Rows */
|
||||
ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* GPIO22/23/24/25/26/27 */
|
||||
ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT) /* GPIO30/31 */
|
||||
@@ -113,6 +113,7 @@ BOARDS_NPCX_SPI=(
|
||||
coral
|
||||
eve
|
||||
fizz
|
||||
glkrvp
|
||||
gru
|
||||
kevin
|
||||
nefario
|
||||
|
||||
Reference in New Issue
Block a user