glados: Initialize PMIC V12 / V0.85A supply

This change is necessary to ensure power-up of edge-case Skylake parts.

BUG=chrome-os-partner:40677
TEST=Manual on Glados. Boot system to S0, run "i2cxfer r 4 0x60 0x38",
verify that 0x7a is read.
BRANCH=None

Change-Id: Id9e62731aaa75fb2357a05d898ba2d4d28f87d9e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274114
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

board/glados/board.c

@@ -7,8 +7,10 @@
 
 #include "button.h"
 #include "charger.h"
+#include "console.h"
 #include "extpower.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "i2c.h"
 #include "lid_switch.h"
 #include "motion_sense.h"
@@ -20,6 +22,8 @@
 #define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
 #define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
 
+#define I2C_ADDR_BD99992 0x60
+
 /* Exchange status with PD MCU. */
 static void pd_mcu_interrupt(enum gpio_signal signal)
 {
@@ -80,3 +84,14 @@ const struct button_config buttons[CONFIG_BUTTON_COUNT] = {
 	{ 0 },
 	{ 0 },
 };
+
+static void pmic_init(void)
+{
+	/*
+	 * Set V085ACNT / V0.85A Control Register:
+	 * Lower power mode = 0.7V.
+	 * Nominal output = 1.0V.
+	 */
+	i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x38, 0x7a);
+}
+DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, pmic_init, HOOK_PRIO_DEFAULT);

board/glados/board.h

@@ -52,6 +52,7 @@
 #define I2C_PORT_PD_MCU MEC1322_I2C1
 #define I2C_PORT_ALS MEC1322_I2C2
 #define I2C_PORT_ACCEL MEC1322_I2C2
+#define I2C_PORT_PMIC MEC1322_I2C3
 
 #ifndef __ASSEMBLER__
 

power/skylake.c

@@ -145,6 +145,9 @@ enum power_state power_handle_state(enum power_state state)
 		break;
 
 	case POWER_G3S5:
+		/* Call hooks to initialize PMIC */
+		hook_notify(HOOK_CHIPSET_PRE_INIT);
+
 		if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
 			chipset_force_shutdown();
 			return POWER_G3;