scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2025-12-28 02:35:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

haswell: fix RCIN# GPIO setting

Browse Source 
The gpio pin used for RCIN# should be configured as open drain as the
rail is pulled up by a non-EC rail. Driving it high would leak power.
The current GPIO_HI_Z macro uses GPIO_HIGH as the default state.
However, it has been found that this actually drives the pin to ground.
It is still unclear how Link works or doesn't.

BUG=chrome-os-partner:19355
BRANCH=none
TEST=manual: boot on slippy without RCIN# causing reset and
     the 'apreset warm' EC command works as expected.

Change-Id: I71425075f8d77b3d7e576a59fc24f823790e2655
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56269
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin
2013-05-22 12:41:08 -05:00
committed by ChromeBot
parent 93ec62ebc3
commit 3ca68b3134
3 changed files with 9 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/slippy/board.c
View File

@@ -95,7 +95,7 @@ const struct gpio_info gpio_list[GPIO_COUNT] = {
{"PCH_NMI_L", LM4_GPIO_F, (1<<2), GPIO_OUT_HIGH, NULL},
{"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL},
{"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
{"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_OUT_HIGH, NULL},
{"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_HI_Z_OPEN, NULL},
{"PCH_RSMRST_L", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL},
{"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL},
{"TOUCHSCREEN_RESET_L", LM4_GPIO_N, (1<<7), GPIO_OUT_LOW, NULL},

10
common/x86_power_haswell.c
View File

@@ -237,10 +237,14 @@ void chipset_reset(int cold_reset)
* PLTRST# to reset the rest of the system.
*/
/* Pulse must be at least 16 PCI clocks long = 500 ns */
gpio_set_level(GPIO_PCH_RCIN_L, 0);
udelay(10);
/*
* Pulse must be at least 16 PCI clocks long = 500 ns. The gpio
* pin used by the EC is configured as open drain. Therefore,
* the driving RCIN# low needs to the level 1 to enable the
* FET and 0 to disable the FET. */
gpio_set_level(GPIO_PCH_RCIN_L, 1);
udelay(10);
gpio_set_level(GPIO_PCH_RCIN_L, 0);
}
}

1
include/gpio.h
View File

@@ -29,6 +29,7 @@
#define GPIO_OUT_LOW (GPIO_OUTPUT | GPIO_LOW)
#define GPIO_OUT_HIGH (GPIO_OUTPUT | GPIO_HIGH)
#define GPIO_HI_Z (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH)
#define GPIO_HI_Z_OPEN (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW)
#define GPIO_INT_EDGE (GPIO_INT_RISING | GPIO_INT_FALLING | GPIO_INT_BOTH)
#define GPIO_INT_LEVEL (GPIO_INT_LOW | GPIO_INT_HIGH)
#define GPIO_INT_ANY (GPIO_INT_EDGE | GPIO_INT_LEVEL)