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strago: Power state transition in case of apshutdown

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In case of 'apshutdown', during transition to S5 state,
GPIO_PCH_SLP_S4_L signal was not getting deasserted but
required rail went away (GPIO_PCH_SYS_PWROK). So it was
going on a loop S5 -> S3 and S3 -> S5.
In strago GPIO_PCH_SYS_PWROK is the PMIC_EN GPIO and hence
conditinally setting it based on CONFIG_PMIC

BUG=none
TEST=apshutdown on strago
BRANCH=none

Change-Id: I9c581a3dfcb9cc84a22b41505e7df496d72d5f4c
Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292024
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Kumar, Gomathi
2015-08-07 16:02:28 +05:30
committed by ChromeOS Commit Bot
parent 3f9ecd30d7
commit 3cbc31aec3
1 changed files with 4 additions and 0 deletions
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4
power/braswell.c
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@@ -61,7 +61,9 @@ void chipset_force_shutdown(void)
* Force power off. This condition will reset once the state machine
* transitions to G3.
*/
#ifndef CONFIG_PMIC
gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
#endif
gpio_set_level(GPIO_PCH_RSMRST_L, 0);
forcing_shutdown = 1;
}
@@ -291,6 +293,8 @@ enum power_state power_handle_state(enum power_state state)
gpio_config_module(MODULE_GPIO, 1);
#ifndef CONFIG_PMIC
gpio_set_level(GPIO_SUSPWRDNACK_SOC_EC, 1);
#else
gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
#endif
forcing_shutdown = 0;