npcx: Add BBRM idx for a 3rd PD port.

Currently, there's only one board with 3 PD ports and it uses NPCX.
Therefore, this commit just adds the index to NPCX which will be used to
save the fact that there was an explicit contract in place.

BUG=b:72838807
BRANCH=None
TEST=make -j buildall

CQ-DEPEND=CL:905390

Change-Id: Ic960f14a52f2a740adbe08bc340c45edfefbbf26
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905922
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

chip/npcx/system.c

@@ -182,7 +182,11 @@ static int bbram_idx_lookup(enum system_bbram_idx idx)
 		return BBRM_DATA_INDEX_PD0;
 	if (idx == SYSTEM_BBRAM_IDX_PD1)
 		return BBRM_DATA_INDEX_PD1;
-#endif
+#if CONFIG_USB_PD_PORT_COUNT >= 3
+	if (idx == SYSTEM_BBRAM_IDX_PD2)
+		return BBRM_DATA_INDEX_PD2;
+#endif /* CONFIG_USB_PD_PORT_COUNT >= 3 */
+#endif /* defined(CONFIG_USB_PD_DUAL_ROLE) */
 #ifdef CONFIG_VBOOT_EFS
 	if (idx == SYSTEM_BBRAM_IDX_TRY_SLOT)
 		return BBRM_DATA_INDEX_TRY_SLOT;

chip/npcx/system_chip.h

@@ -20,6 +20,7 @@ enum bbram_data_index {
 	BBRM_DATA_INDEX_PD0 = 12,	       /* USB-PD saved port0 state */
 	BBRM_DATA_INDEX_PD1 = 13,	       /* USB-PD saved port1 state */
 	BBRM_DATA_INDEX_TRY_SLOT = 14,         /* Vboot EC try slot */
+	BBRM_DATA_INDEX_PD2 = 15,	       /* USB-PD saved port2 state */
 	BBRM_DATA_INDEX_VBNVCNTXT = 16,	       /* VbNvContext for ARM arch */
 	BBRM_DATA_INDEX_RAMLOG = 32,	       /* RAM log for Booter */
 	BBRM_DATA_INDEX_PANIC_FLAGS = 35,      /* Flag to indicate validity of

include/system.h

@@ -341,6 +341,7 @@ enum system_bbram_idx {
 	/* PD state for CONFIG_USB_PD_DUAL_ROLE uses one byte per port */
 	SYSTEM_BBRAM_IDX_PD0,
 	SYSTEM_BBRAM_IDX_PD1,
+	SYSTEM_BBRAM_IDX_PD2,
 	SYSTEM_BBRAM_IDX_TRY_SLOT,
 };