scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2026-01-13 03:15:06 +00:00
Code Issues Packages Projects Releases Wiki Activity

intel_x86: Move chipset reset logic to common code

Browse Source 
Chipset reset logic chipset_reset() is same for APL, GLK,
SKL, KBL and CNL hence move it to common code.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j

Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974471
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Vijay Hiremath
2018-03-21 13:54:59 -07:00
committed by chrome-bot
parent e94bf79f85
commit 3e12d9af20
4 changed files with 31 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
power/apollolake.c
View File

@@ -37,18 +37,6 @@ void chipset_handle_espi_reset_assert(void)
{
}
void chipset_reset(int cold_reset)
{
CPRINTS("%s", __func__);
/*
* Send a pulse to SOC PMU_RSTBTN_N to trigger a warm reset.
*/
gpio_set_level(GPIO_SYS_RESET_L, 0);
usleep(32 * MSEC);
gpio_set_level(GPIO_SYS_RESET_L, 1);
}
static void handle_all_sys_pgood(enum power_state state)
{
/*

20
power/cannonlake.c
View File

@@ -52,26 +52,6 @@ void chipset_handle_espi_reset_assert(void)
}
}
void chipset_reset(int cold_reset)
{
/*
* The EC cannot control warm vs cold reset of the chipset using
* SYS_RESET_L; it's more of a request.
*/
CPRINTS("%s()", __func__);
if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
return;
/*
* Debounce time for SYS_RESET_L is 16 ms. Wait twice that period to be
* safe.
*/
gpio_set_level(GPIO_SYS_RESET_L, 0);
udelay(32 * MSEC);
gpio_set_level(GPIO_SYS_RESET_L, 1);
}
enum power_state chipset_force_g3(void)
{
int timeout = 50;

31
power/intel_x86.c
View File

@@ -509,3 +509,34 @@ void power_chipset_handle_host_sleep_event(enum host_sleep_event state)
}
#endif
void chipset_reset(int cold_reset)
{
/*
* Irrespective of cold_reset value, always toggle SYS_RESET_L to
* perform a chipset reset. RCIN# which was used earlier to trigger
* a warm reset is known to not work in certain cases where the CPU
* is in a bad state (crbug.com/721853).
*
* The EC cannot control warm vs cold reset of the chipset using
* SYS_RESET_L; it's more of a request.
*/
CPRINTS("%s", __func__);
/*
* Toggling SYS_RESET_L will not have any impact when it's already
* low (i,e. Chipset is in reset state).
*/
if (gpio_get_level(GPIO_SYS_RESET_L) == 0) {
CPRINTS("Chipset is in reset state");
return;
}
gpio_set_level(GPIO_SYS_RESET_L, 0);
/*
* Debounce time for SYS_RESET_L is 16 ms. Wait twice that period
* to be safe.
*/
udelay(32 * MSEC);
gpio_set_level(GPIO_SYS_RESET_L, 1);
}

18
power/skylake.c
View File

@@ -54,24 +54,6 @@ enum power_state chipset_force_g3(void)
return POWER_G3;
}
void chipset_reset(int cold_reset)
{
CPRINTS("%s(%d)", __func__, cold_reset);
/*
* Irrespective of cold_reset value, always toggle SYS_RESET_L to
* perform a chipset reset. RCIN# which was used earlier to trigger a
* warm reset is known to not work in certain cases where the CPU is in
* a bad state (crbug.com/721853)
*/
if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
return;
gpio_set_level(GPIO_SYS_RESET_L, 0);
/* Debounce time for SYS_RESET_L is 16 ms */
udelay(20 * MSEC);
gpio_set_level(GPIO_SYS_RESET_L, 1);
}
static void handle_slp_sus(enum power_state state)
{
/* If we're down or going down don't do anythin with SLP_SUS_L. */