add the skeleton for STM32L chip and discovery board

All hardware drivers code is stubbed excepted a few configuration
settings.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=make BOARD=discovery

Change-Id: Ic9e88a0f51ab626679c8aeb6192272e66a3f79b8

board/discovery/board.c

@@ -0,0 +1,46 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* STM32L Discovery board-specific configuration */
+
+#include "board.h"
+#include "common.h"
+
+void configure_board(void)
+{
+}
+
+/**
+ * Stubs for non implemented drivers
+ * TODO: implement
+ */
+int jtag_pre_init(void)
+{
+	return EC_SUCCESS;
+}
+
+int gpio_pre_init(void)
+{
+	return EC_SUCCESS;
+}
+
+int eeprom_init(void)
+{
+	return EC_SUCCESS;
+}
+
+int i2c_init(void)
+{
+	return EC_SUCCESS;
+}
+
+int power_button_init(void)
+{
+	return EC_SUCCESS;
+}
+
+int adc_init(void)
+{
+	return EC_SUCCESS;
+}

board/discovery/board.h

@@ -0,0 +1,24 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* STM32L Discovery board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+#define USB_CHARGE_PORT_COUNT 0
+
+/* GPIO signal list */
+enum gpio_signal {
+	GPIO_DUMMY0 = 0,   /* Dummy GPIO */
+	GPIO_DUMMY1,
+
+	/* Number of GPIOs; not an actual GPIO */
+	GPIO_COUNT
+};
+
+void configure_board(void);
+
+#endif /* __BOARD_H */

board/discovery/build.mk

@@ -0,0 +1,10 @@
+# Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32L151R8H6
+CHIP:=stm32l
+
+board-y=board.o

board/discovery/ec.tasklist

@@ -0,0 +1,17 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK(n, r, d) where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ */
+#define CONFIG_TASK_LIST \
+	TASK(CONSOLE, console_task, NULL)

chip/stm32l/build.mk

@@ -0,0 +1,11 @@
+# Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# STM32L chip specific files build
+#
+
+# STM32L15xx SoC family has a Cortex-M3 ARM core
+CORE:=cortex-m
+
+chip-y=uart.o clock.o hwtimer.o system.o

chip/stm32l/clock.c

@@ -0,0 +1,29 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks and power management settings */
+
+#include <stdint.h>
+
+#include "clock.h"
+#include "common.h"
+
+/**
+ * Idle task
+ * executed when no task are ready to be scheduled
+ */
+void __idle(void)
+{
+	while (1) {
+		/* wait for the irq event */
+		asm("wfi");
+		/* TODO more power management here */
+	}
+}
+
+int clock_init(void)
+{
+	return EC_SUCCESS;
+}

chip/stm32l/config.h

@@ -0,0 +1,35 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Memory mapping */
+#define CONFIG_FLASH_BASE       0x08000000
+#define CONFIG_FLASH_SIZE       0x00020000
+#define CONFIG_FLASH_BANK_SIZE  0x1000
+#define CONFIG_RAM_BASE         0x20000000
+#define CONFIG_RAM_SIZE         0x00004000
+
+/* Size of one firmware image in flash */
+#define CONFIG_FW_IMAGE_SIZE    (32 * 1024)
+#define CONFIG_FW_RO_OFF        0
+#define CONFIG_FW_A_OFF         CONFIG_FW_IMAGE_SIZE
+#define CONFIG_FW_B_OFF         (2 * CONFIG_FW_IMAGE_SIZE)
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT 45
+
+/* Debug UART parameters for panic message */
+#define CONFIG_UART_ADDRESS    0x40013800
+#define CONFIG_UART_DR_OFFSET  0x04
+#define CONFIG_UART_SR_OFFSET  0x00
+#define CONFIG_UART_SR_TXEMPTY 0x80
+
+/* System stack size */
+#define CONFIG_STACK_SIZE 1024
+
+/* build with assertions and debug messages */
+#define CONFIG_DEBUG
+
+/* Compile for running from RAM instead of flash */
+/* #define COMPILE_FOR_RAM */

chip/stm32l/hwtimer.c

@@ -0,0 +1,35 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Hardware timers driver */
+
+#include <stdint.h>
+
+#include "board.h"
+#include "hwtimer.h"
+#include "task.h"
+
+void __hw_clock_event_set(uint32_t deadline)
+{
+}
+
+uint32_t __hw_clock_event_get(void)
+{
+	return 0;
+}
+
+void __hw_clock_event_clear(void)
+{
+}
+
+uint32_t __hw_clock_source_read(void)
+{
+	return 0;
+}
+
+int __hw_clock_source_init(void)
+{
+	return -1;
+}

chip/stm32l/system.c

@@ -0,0 +1,65 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* System module for Chrome EC : hardware specific implementation */
+
+#include "cpu.h"
+#include "system.h"
+
+
+static void check_reset_cause(void)
+{
+	system_set_reset_cause(SYSTEM_RESET_UNKNOWN);
+}
+
+
+void system_hibernate(uint32_t seconds, uint32_t microseconds)
+{
+	/* we are going to hibernate ... */
+	while (1)
+		;
+}
+
+
+int system_pre_init(void)
+{
+	check_reset_cause();
+
+	return EC_SUCCESS;
+}
+
+
+int system_init(void)
+{
+	return EC_SUCCESS;
+}
+
+
+int system_reset(int is_cold)
+{
+	/* TODO: (crosbug.com/p/7470) support cold boot; this is a
+	   warm boot. */
+	CPU_NVIC_APINT = 0x05fa0004;
+
+	/* Spin and wait for reboot; should never return */
+	/* TODO: (crosbug.com/p/7471) should disable task swaps while
+	   waiting */
+	while (1)
+		;
+
+	return EC_ERROR_UNKNOWN;
+}
+
+
+int system_set_scratchpad(uint32_t value)
+{
+	return EC_SUCCESS;
+}
+
+
+uint32_t system_get_scratchpad(void)
+{
+	return 0xdeadbeef;
+}

chip/stm32l/uart.c

@@ -0,0 +1,63 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USART driver for Chrome EC */
+
+#include <stdarg.h>
+
+#include "task.h"
+#include "uart.h"
+
+/* Baud rate for UARTs */
+#define BAUD_RATE 115200
+
+void uart_tx_start(void)
+{
+}
+
+void uart_tx_stop(void)
+{
+}
+
+int uart_tx_stopped(void)
+{
+	return 0;
+}
+
+void uart_tx_flush(void)
+{
+}
+
+int uart_tx_ready(void)
+{
+	return 1;
+}
+
+int uart_rx_available(void)
+{
+	return 0;
+}
+
+void uart_write_char(char c)
+{
+}
+
+int uart_read_char(void)
+{
+	return 0;
+}
+
+void uart_disable_interrupt(void)
+{
+}
+
+void uart_enable_interrupt(void)
+{
+}
+
+int uart_init(void)
+{
+	return EC_SUCCESS;
+}