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Fizz: Enable/disable USB Type-A ports

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This change makes Fizz enable USB type-A ports on resume and disable
them on shutdown.

BUG=b:38226666
BRANCH=none
TEST=Boot Fizz off of USB flash drive on a USB-A port.

Change-Id: I7f22438271ffc080e950f5f300937d89706e08a4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481078
This commit is contained in:
Daisuke Nojiri
2017-04-17 11:37:18 -07:00
committed by chrome-bot
parent bb1b65a177
commit 44b9f9df83
3 changed files with 18 additions and 0 deletions
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8
board/fizz/board.c
View File

@@ -128,6 +128,14 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = {
}
};
const int usb_port_enable[USB_PORT_COUNT] = {
GPIO_USB1_ENABLE,
GPIO_USB2_ENABLE,
GPIO_USB3_ENABLE,
GPIO_USB4_ENABLE,
GPIO_USB5_ENABLE,
};
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0);

4
board/fizz/board.h
View File

@@ -117,6 +117,10 @@
#define CONFIG_USBC_VCONN
#define CONFIG_USBC_VCONN_SWAP
/* USB-A config */
#define CONFIG_USB_PORT_POWER_DUMB
#define USB_PORT_COUNT 5
/* Optional feature to configure npcx chip */
#define NPCX_UART_MODULE2 1 /* 1:GPIO64/65 as UART */
#define NPCX_JTAG_MODULE2 0 /* 0:GPIO21/17/16/20 as JTAG */

6
board/fizz/gpio.inc
View File

@@ -77,6 +77,12 @@ GPIO(USB_C0_PD_RST_ODL, PIN(0, 3), GPIO_OUT_LOW) /* C0 PD Reset */
GPIO(USB_C0_DP_HPD, PIN(9, 4), GPIO_INPUT) /* C0 DP Hotplug Detect */
GPIO(USB_C0_TCPC_PWR, PIN(8, 4), GPIO_OUT_LOW) /* Enable C0 TCPC Power */
GPIO(FAN_PWR_EN, PIN(9, 5), GPIO_OUT_HIGH) /* Fan power */
GPIO(USB1_ENABLE, PIN(3, 2), GPIO_OUT_LOW) /* Rear port, bottom */
GPIO(USB2_ENABLE, PIN(C, 6), GPIO_OUT_LOW) /* Rear port, top */
GPIO(USB3_ENABLE, PIN(A, 1), GPIO_OUT_LOW) /* Rear port, single */
GPIO(USB4_ENABLE, PIN(0, 0), GPIO_OUT_LOW) /* Front port 1 */
GPIO(USB5_ENABLE, PIN(B, 1), GPIO_OUT_LOW) /* Front port 2 */
GPIO(USB_A_CHARGE_EN_L, PIN(A, 5), GPIO_OUT_LOW)
/* Board ID */
GPIO(BOARD_VERSION1, PIN(C, 4), GPIO_INPUT) /* Board ID bit0 */