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AMD Trinity boards: Add reserved memory area for SPI base address in ACPI

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- SPI controller base address gets overwritten by SD controller under Linux.

    - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't
      get automatically reserved. Solution is to add it as a reserved memory area in
      ACPI.

    - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this
      platform was made as part of: http://review.coreboot.org/#/c/3167/3

    - Once approved a follow-on patch for other southbridges using a non-standard BAR for
      the spi controller.

Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/3270
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Steven Sherk
2013-05-22 13:49:18 -06:00
committed by Ronald G. Minnich
parent 0390112407
commit 474eeedbc8
3 changed files with 81 additions and 0 deletions
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27
src/mainboard/amd/parmer/dsdt.asl
View File

@@ -1251,6 +1251,33 @@ DefinitionBlock (
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
} */ /* End Method(_SB.SBRDG._INI) */
OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
Field(CFG,DWordAcc,NoLock,Preserve){
Offset(0xA0),
BAR,32} // SPI Controller Base Address Register (Index 0xA0)
Device(LDRC) // LPC device: Resource consumption
{
Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
Name (CRS, ResourceTemplate () // Current Motherboard resources
{
Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
0x00000000, // Address Base
0x00000000, // Address Length
BAR0 // Descriptor Name
)
})
Method(_CRS,0,NotSerialized)
{
CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
Store(BAR,SPIB) // SPI base address mapped
Store(0x1000,SPIL) // 4k space mapped
Return(CRS)
}
}
/* Real Time Clock Device */
Device(RTC0) {
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */

27
src/mainboard/amd/thatcher/dsdt.asl
View File

@@ -1242,6 +1242,33 @@ DefinitionBlock (
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
} */ /* End Method(_SB.SBRDG._INI) */
OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
Field(CFG,DWordAcc,NoLock,Preserve){
Offset(0xA0),
BAR,32} // SPI Controller Base Address Register (Index 0xA0)
Device(LDRC) // LPC device: Resource consumption
{
Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
Name (CRS, ResourceTemplate () // Current Motherboard resources
{
Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
0x00000000, // Address Base
0x00000000, // Address Length
BAR0 // Descriptor Name
)
})
Method(_CRS,0,NotSerialized)
{
CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
Store(BAR,SPIB) // SPI base address mapped
Store(0x1000,SPIL) // 4k space mapped
Return(CRS)
}
}
/* Real Time Clock Device */
Device(RTC0) {
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */

27
src/mainboard/asus/f2a85-m/dsdt.asl
View File

@@ -1235,6 +1235,33 @@ DefinitionBlock (
* DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
} */ /* End Method(_SB.SBRDG._INI) */
OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space
Field(CFG,DWordAcc,NoLock,Preserve){
Offset(0xA0),
BAR,32} // SPI Controller Base Address Register (Index 0xA0)
Device(LDRC) // LPC device: Resource consumption
{
Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources
Name (CRS, ResourceTemplate () // Current Motherboard resources
{
Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address
0x00000000, // Address Base
0x00000000, // Address Length
BAR0 // Descriptor Name
)
})
Method(_CRS,0,NotSerialized)
{
CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address
CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length
Store(BAR,SPIB) // SPI base address mapped
Store(0x1000,SPIL) // 4k space mapped
Return(CRS)
}
}
/* Real Time Clock Device */
Device(RTC0) {
Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */