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oak_pd: add initial support for oak PD
Add initial support for Oak PD MCU on rev1 boards. This does not include USB PD communication. BUG=none BRANCH=none TEST=build and load on oak and get console. test we resond to host commands from EC using "pdcmd 0 0" on EC console. Change-Id: I92045cf0fd682279ada6c286f5399f0e258a6305 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271828
This commit is contained in:
Alec Berg
committed by
ChromeOS Commit Bot
ChromeOS Commit Bot
parent
97934e4041
commit
488f8c9565
1
board/oak_pd/Makefile
Symbolic link
1
board/oak_pd/Makefile
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@@ -0,0 +1 @@
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../../Makefile
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108
board/oak_pd/board.c
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108
board/oak_pd/board.c
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@@ -0,0 +1,108 @@
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* oak_pd board configuration */
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#include "adc.h"
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#include "adc_chip.h"
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#include "common.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "host_command.h"
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#include "i2c.h"
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#include "registers.h"
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#include "system.h"
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#include "task.h"
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#include "util.h"
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#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
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void pd_send_ec_int(void)
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{
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gpio_set_level(GPIO_EC_INT, 0);
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/*
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* Delay long enough to guarantee EC see's the change.
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* TODO: make sure this delay is sufficient.
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*/
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usleep(5);
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gpio_set_level(GPIO_EC_INT, 1);
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}
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void vbus0_evt(enum gpio_signal signal)
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{
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#ifdef HAS_TASK_PD_C0
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task_wake(TASK_ID_PD_C0);
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#endif
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}
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void vbus1_evt(enum gpio_signal signal)
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{
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#ifdef HAS_TASK_PD_C1
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task_wake(TASK_ID_PD_C1);
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#endif
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}
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void board_config_pre_init(void)
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{
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/* enable SYSCFG clock */
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STM32_RCC_APB2ENR |= 1 << 0;
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/*
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* the DMA mapping is :
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* Chan 2 : TIM1_CH1 (C0 RX)
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* Chan 3 : SPI1_TX (C0 TX)
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* Chan 4 : TIM3_CH1 (C1 RX)
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* Chan 5 : SPI2_TX (C1 TX)
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*/
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}
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#include "gpio_list.h"
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/* Initialize board. */
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static void board_init(void)
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{
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/* Enable interrupts on VBUS transitions. */
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gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
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gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
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/* OAK_PD: TODO: Power management of ARM based system */
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}
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DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
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/* ADC channels */
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const struct adc_t adc_channels[] = {
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/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
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[ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
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[ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
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[ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
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[ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
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};
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BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
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/* I2C ports */
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const struct i2c_port_t i2c_ports[] = {
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{"slave", I2C_PORT_SLAVE, 1000, GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA}
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};
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const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
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void tcpc_alert(void)
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{
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pd_send_ec_int();
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}
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/****************************************************************************/
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/* Console commands */
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static int command_ec_int(int argc, char **argv)
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{
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pd_send_ec_int();
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return EC_SUCCESS;
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}
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DECLARE_CONSOLE_COMMAND(ecint, command_ec_int,
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"",
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"Toggle EC interrupt line",
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NULL);
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94
board/oak_pd/board.h
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94
board/oak_pd/board.h
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@@ -0,0 +1,94 @@
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* oak_pd board configuration */
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#ifndef __BOARD_H
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#define __BOARD_H
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/*
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* The flash size is only 32kB.
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* No space for 2 partitions,
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* put only RW at the beginning of the flash
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*/
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#undef CONFIG_FW_INCLUDE_RO
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#undef CONFIG_RW_MEM_OFF
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#define CONFIG_RW_MEM_OFF 0
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#undef CONFIG_RO_SIZE
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#define CONFIG_RO_SIZE 0
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/* Fake full size if we had a RO partition */
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#undef CONFIG_FW_IMAGE_SIZE
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#define CONFIG_FW_IMAGE_SIZE (64*1024)
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/* 48 MHz SYSCLK clock frequency */
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#define CPU_CLOCK 48000000
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/* the UART console is on USART1 (PA9/PA10) */
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#undef CONFIG_UART_CONSOLE
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#define CONFIG_UART_CONSOLE 1
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/* Optional features */
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#define CONFIG_ADC
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#define CONFIG_BOARD_PRE_INIT
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#undef CONFIG_CMD_I2C_SCAN
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#undef CONFIG_CMD_I2C_XFER
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#undef CONFIG_CMD_IDLE_STATS
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#undef CONFIG_CMD_SHMEM
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#define CONFIG_COMMON_GPIO_SHORTNAMES
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#define CONFIG_CONSOLE_CMDHELP
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#define CONFIG_CONSOLE_HISTORY 3
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#undef CONFIG_DEBUG_ASSERT
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#define CONFIG_FORCE_CONSOLE_RESUME
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#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP2)
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#undef CONFIG_HOSTCMD_EVENTS
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#define CONFIG_HW_CRC
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#define CONFIG_I2C
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#undef CONFIG_LID_SWITCH
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#undef CONFIG_LOW_POWER_IDLE
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#define CONFIG_STM_HWTIMER32
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#undef CONFIG_TASK_PROFILING
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#undef CONFIG_UART_TX_BUF_SIZE
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#undef CONFIG_UART_TX_DMA
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#undef CONFIG_UART_RX_DMA
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#define CONFIG_UART_TX_BUF_SIZE 128
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#define CONFIG_VBOOT_HASH
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#undef CONFIG_WATCHDOG
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#undef CONFIG_WATCHDOG_HELP
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/* Use PSTATE embedded in the RO image, not in its own erase block */
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#undef CONFIG_FLASH_PSTATE_BANK
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#undef CONFIG_FW_PSTATE_SIZE
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#define CONFIG_FW_PSTATE_SIZE 0
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/* I2C ports configuration */
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#define I2C_PORT_SLAVE 0
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#define I2C_PORT_EC I2C_PORT_SLAVE
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/* slave address for host commands */
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#ifdef HAS_TASK_HOSTCMD
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#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR CONFIG_USB_PD_I2C_SLAVE_ADDR
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#endif
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#ifndef __ASSEMBLER__
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/* Timer selection */
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#define TIM_CLOCK32 2
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#define TIM_ADC 3
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#include "gpio_signal.h"
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/* ADC signal */
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enum adc_channel {
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ADC_C1_CC1_PD = 0,
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ADC_C0_CC1_PD,
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ADC_C0_CC2_PD,
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ADC_C1_CC2_PD,
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/* Number of ADC channels */
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ADC_CH_COUNT
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};
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#endif /* !__ASSEMBLER__ */
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#endif /* __BOARD_H */
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13
board/oak_pd/build.mk
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13
board/oak_pd/build.mk
Normal file
@@ -0,0 +1,13 @@
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# -*- makefile -*-
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# Copyright 2015 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# Board specific files build
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# the IC is STmicro STM32F051C8T
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CHIP:=stm32
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CHIP_FAMILY:=stm32f0
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CHIP_VARIANT:=stm32f05x
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board-y=board.o
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22
board/oak_pd/ec.tasklist
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22
board/oak_pd/ec.tasklist
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@@ -0,0 +1,22 @@
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/**
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* List of enabled tasks in the priority order
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*
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* The first one has the lowest priority.
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*
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* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
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* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
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* where :
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* 'n' in the name of the task
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* 'r' in the main routine of the task
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* 'd' in an opaque parameter passed to the routine at startup
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* 's' is the stack size in bytes; must be a multiple of 8
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*/
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#define CONFIG_TASK_LIST \
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TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_NOTEST(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
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64
board/oak_pd/gpio.inc
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64
board/oak_pd/gpio.inc
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@@ -0,0 +1,64 @@
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/* -*- mode:c -*-
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*
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* Copyright 2015 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Interrupts */
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GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(C, 14), GPIO_INT_BOTH, vbus0_evt)
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GPIO_INT(USB_C1_VBUS_WAKE_L, PIN(C, 15), GPIO_INT_BOTH, vbus1_evt)
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/* PD RX/TX */
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GPIO(USB_C0_CC1_PD, PIN(A, 2), GPIO_ANALOG)
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GPIO(USB_C_REF, PIN(A, 1), GPIO_ANALOG)
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GPIO(USB_C1_CC1_PD, PIN(A, 0), GPIO_ANALOG)
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GPIO(USB_C0_CC2_PD, PIN(A, 4), GPIO_ANALOG)
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GPIO(USB_C1_CC2_PD, PIN(A, 5), GPIO_ANALOG)
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GPIO(USB_C1_CCX_TX_DATA, PIN(B, 14), GPIO_INPUT)
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GPIO(USB_C0_CC1_TX_DATA, PIN(B, 4), GPIO_INPUT)
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GPIO(USB_C1_CC2_TX_SEL, PIN(B, 0), GPIO_OUT_LOW) /* C1_CC2_TX_SEL */
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GPIO(USB_C0_CC2_TX_DATA, PIN(A, 6), GPIO_INPUT)
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GPIO(USB_PD_VBUS_WAKE, PIN(C, 13), GPIO_INPUT)
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GPIO(PP3300_USB_PD_EN, PIN(A, 15), GPIO_OUT_HIGH)
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GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1), GPIO_OUT_LOW)
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GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2), GPIO_OUT_LOW)
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GPIO(USB_C1_CC1_VCONN1_EN, PIN(B, 9), GPIO_OUT_LOW)
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GPIO(USB_C1_CC2_VCONN1_EN, PIN(F, 0), GPIO_OUT_LOW)
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GPIO(USB_C0_HOST_HIGH, PIN(A, 3), GPIO_OUT_LOW)
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GPIO(USB_C1_HOST_HIGH, PIN(A, 7), GPIO_OUT_LOW)
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GPIO(USB_C0_CC1_ODL, PIN(A, 11), GPIO_ODR_LOW)
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GPIO(USB_C0_CC2_ODL, PIN(A, 12), GPIO_ODR_LOW)
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GPIO(USB_C1_CC1_ODL, PIN(B, 12), GPIO_ODR_LOW)
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GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW)
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/*
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* I2C pins should be configured as inputs until I2C module is
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* initialized. This will avoid driving the lines unintentionally.
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*/
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GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT)
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GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT)
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/* Case closed debugging. */
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GPIO(EC_INT, PIN(A, 14), GPIO_OUT_HIGH)
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GPIO(TP_194, PIN(B, 5), GPIO_OUT_LOW)
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UNIMPLEMENTED(WP_L)
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UNIMPLEMENTED(ENTERING_RW)
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#if 0
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/* Alternate functions */
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GPIO(USB_C1_TX_CLKOUT, PIN(B, 15), GPIO_OUT_LOW)
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GPIO(USB_C0_TX_CLKOUT, PIN(B, 8), GPIO_OUT_LOW)
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GPIO(USB_C1_TX_CLKIN, PIN(B, 13), GPIO_OUT_LOW)
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GPIO(USB_C0_TX_CLKIN, PIN(B, 3), GPIO_OUT_LOW)
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#endif
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ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
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ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */
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ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8 */
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ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15 */
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ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */
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ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */
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@@ -46,6 +46,8 @@ static int dsleep_recovery_margin_us = 1000000;
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*/
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#ifdef CHIP_VARIANT_STM32F373
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#define STOP_MODE_LATENCY 500 /* us */
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#elif defined(CHIP_VARIANT_STM32F05X)
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#define STOP_MODE_LATENCY 300 /* us */
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#elif (CPU_CLOCK == PLL_CLOCK)
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#define STOP_MODE_LATENCY 300 /* us */
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#else
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@@ -245,6 +247,45 @@ static void config_hispeed_clock(void)
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/* Wait until the PLL is the clock source */
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while ((STM32_RCC_CFGR & 0xc) != 0x8)
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;
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#elif defined(CHIP_VARIANT_STM32F05X)
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/* If PLL is the clock source, PLL has already been set up. */
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if ((STM32_RCC_CFGR & 0xc) == 0x8)
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return;
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/* Ensure that HSI is ON */
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if (!(STM32_RCC_CR & (1<<1))) {
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/* Enable HSI */
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STM32_RCC_CR |= (1<<0);
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/* Wait for HSI to be ready */
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while (!(STM32_RCC_CR & (1<<1)))
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;
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}
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/*
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* HSI = 8MHz, HSI/2 with PLL *12 = ~48 MHz
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* therefore PCLK = FCLK = SYSCLK = 48MHz
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*/
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/* Switch the PLL source to HSI/2 */
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STM32_RCC_CFGR &= ~(0x00018000);
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/*
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* Specify HSI/2 clock as input clock to PLL and set PLL (*12).
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*/
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STM32_RCC_CFGR |= 0x00280000;
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/* Enable the PLL. */
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STM32_RCC_CR |= 0x01000000;
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/* Wait until PLL is ready. */
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while (!(STM32_RCC_CR & 0x02000000))
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;
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/* Switch SYSCLK to PLL. */
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STM32_RCC_CFGR |= 0x2;
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/* wait until the PLL is the clock source */
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while ((STM32_RCC_CFGR & 0xc) != 0x8)
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;
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#else
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/* Ensure that HSI48 is ON */
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if (!(STM32_RCC_CR2 & (1 << 17))) {
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24
chip/stm32/config-stm32f05x.h
Normal file
24
chip/stm32/config-stm32f05x.h
Normal file
@@ -0,0 +1,24 @@
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
|
||||
* Use of this source code is governed by a BSD-style license that can be
|
||||
* found in the LICENSE file.
|
||||
*/
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/* Memory mapping */
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#define CONFIG_FLASH_BASE 0x08000000
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#define CONFIG_FLASH_PHYSICAL_SIZE (64 * 1024)
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#define CONFIG_FLASH_BANK_SIZE 0x1000
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#define CONFIG_FLASH_ERASE_SIZE 0x0800 /* erase bank size */
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#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
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/* No page mode on STM32F, so no benefit to larger write sizes */
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#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
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#define CONFIG_RAM_BASE 0x20000000
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#define CONFIG_RAM_SIZE 0x00002000
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/* Number of IRQ vectors on the NVIC */
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#define CONFIG_IRQ_COUNT 32
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/* Reduced history because of limited RAM */
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#undef CONFIG_CONSOLE_HISTORY
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#define CONFIG_CONSOLE_HISTORY 3
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@@ -36,6 +36,9 @@
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#elif defined(CHIP_VARIANT_STM32F07X)
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/* STM32F07xx */
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#include "config-stm32f07x.h"
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#elif defined(CHIP_VARIANT_STM32F05X)
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/* STM32F05xx */
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#include "config-stm32f05x.h"
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#elif defined(CHIP_VARIANT_STM32F03X)
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/* STM32F03x */
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#include "config-stm32f03x.h"
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@@ -28,6 +28,7 @@ test-list-$(BOARD_LLAMA)=
|
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# For some tests, we are running out of RAM for Samus PD. Disable them for
|
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# now.
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test-list-$(BOARD_SAMUS_PD)=
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test-list-$(BOARD_OAK_PD)=
|
||||
|
||||
# Emulator tests
|
||||
test-list-host=mutex pingpong utils kb_scan kb_mkbp lid_sw power_button hooks
|
||||
|
||||
Reference in New Issue
Block a user