Celes: Add define to support GD25Q41B for External EC ROM.

MEC1322 use external spi rom. Now, we support W25X40 and W25Q64.
Celes will use GD25Q41B for external EC ROM.
So, we need to add define for GD25Q41B.

BUG=chrome-os-partner:45246
BRANCH=master
TEST=emerge-strago chromeos-ec

Change-Id: Idec79955306b2dd79027fa57afc15ed8474413e6
Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/299576
Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.com>
Tested-by: Jongpil Jung <jongpil19.jung@samsung.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
jongpil19.jung
2015-09-15 09:46:14 +09:00
committed by chrome-bot
parent 3154abd5c3
commit 4b3c13ddfe
3 changed files with 5 additions and 2 deletions

View File

@@ -37,7 +37,7 @@ struct protect_range {
* none or half of the ROM. The table is searched sequentially, so ordering
* according to likely configurations improves performance slightly.
*/
#ifdef CONFIG_SPI_FLASH_W25X40
#if defined(CONFIG_SPI_FLASH_W25X40) || defined(CONFIG_SPI_FLASH_GD25Q41B)
static const struct protect_range spi_flash_protect_ranges[] = {
{ X, X, X, { 0, 0, 0 }, 0, 0 }, /* No protection */
{ X, X, 1, { 0, 1, 1 }, 0, 0x40000 }, /* Lower 1/2 */

View File

@@ -1427,6 +1427,9 @@
/* Support W25X40 SPI flash */
#undef CONFIG_SPI_FLASH_W25X40
/* Support GD25Q41B SPI flash */
#undef CONFIG_SPI_FLASH_GD25Q41B
/* SPI flash part supports SR2 register */
#undef CONFIG_SPI_FLASH_HAS_SR2

View File

@@ -34,7 +34,7 @@
/* SR2 register existence based upon chip */
#ifdef CONFIG_SPI_FLASH_W25X40
#undef CONFIG_SPI_FLASH_HAS_SR2
#elif defined(CONFIG_SPI_FLASH_W25Q64)
#elif defined(CONFIG_SPI_FLASH_W25Q64) || defined(CONFIG_SPI_FLASH_GD25Q41B)
#define CONFIG_SPI_FLASH_HAS_SR2
#endif