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npcx: Fixed host access pending bit issue in INT11 ISR.

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Since the pending bit of host access interrupt is set frequently if
PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering
S0. It's better to add checking enable bit of MIWU of it in case huge
latency between gpio interrupt and serving its own ISR in INT11's ISR.

Modified sources:
1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR.

BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers

Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/352362
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Mulin Chao
2016-06-14 14:22:21 +08:00
committed by chrome-bot
parent aff5c83053
commit 4bb0efcc28
1 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
chip/npcx/gpio.c
View File

@@ -788,16 +788,16 @@ void __gpio_wk0efgh_interrupt(void)
{
#ifdef CONFIG_LPC
/* Pending bit 7 or 6 ? */
if (NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5) & 0xC0) {
if (IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 6)) {
/* Clear pending bit of WUI */
SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 6);
/* Disable host wake-up */
CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
}
if (IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 7))
lpc_lreset_pltrst_handler();
} else
if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 6) &&
IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 6)) {
/* Disable host wake-up */
CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6);
/* Clear pending bit of WUI */
SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 6);
} else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 7) &&
IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 7))
lpc_lreset_pltrst_handler();
else /* FW will jump into ISR again if other GPIOs' INT still issued */
#endif
gpio_interrupt(NPCX_IRQ_WKINTEFGH_0);
}