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stm32: Clean up JTAG registers

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No functional changes, just cleanup.

BUG=chrome-os-partner:20529
BRANCH=none
TEST=boot pit

Change-Id: I2067dffc3b1335f001a95e63b22213a1022f3ae8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61095
This commit is contained in:
ChromeOS Developer
2013-07-03 11:43:29 -07:00
committed by ChromeBot
parent b013fd4e9c
commit 4e31062449
3 changed files with 30 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
chip/stm32/hwtimer.c
View File

@@ -165,21 +165,25 @@ void __hw_timer_enable_clock(int n, int enable)
volatile uint32_t *reg;
uint32_t mask = 0;
/*
* Mapping of timers to reg/mask is split into a few different ranges,
* some specific to individual chips.
*/
#if defined(CHIP_FAMILY_stm32f)
if (n == 1) {
reg = &STM32_RCC_APB2ENR;
mask = 1 << 11;
mask = STM32_RCC_PB2_TIM1;
}
#elif defined(CHIP_FAMILY_stm32l)
if (n >= 9 && n <= 11) {
reg = &STM32_RCC_APB2ENR;
mask = 1 << (n - 7);
mask = STM32_RCC_PB2_TIM9 << (n - 9);
}
#endif
if (n >= 2 && n <= 7) {
reg = &STM32_RCC_APB1ENR;
mask = 1 << (n - 2);
mask = STM32_RCC_PB1_TIM2 << (n - 2);
}
if (!mask)

11
chip/stm32/jtag-stm32l.c
View File

@@ -9,6 +9,13 @@
void jtag_pre_init(void)
{
/* stop TIM2-4 and watchdogs when the JTAG stops the CPU */
STM32_DBGMCU_APB1FZ |= 0x00001807;
/*
* Stop all timers we might use (TIM2-4,9-11) and watchdogs when
* the JTAG stops the CPU.
*/
STM32_DBGMCU_APB1FZ |=
STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM4 |
STM32_RCC_PB1_WWDG | STM32_RCC_PB1_IWDG;
STM32_DBGMCU_APB2FZ |= STM32_RCC_PB2_TIM9 | STM32_RCC_PB2_TIM10 |
STM32_RCC_PB2_TIM11;
}

15
chip/stm32/registers.h
View File

@@ -347,6 +347,9 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34)
#define STM32_RCC_HB_DMA1 (1 << 24)
#define STM32_RCC_PB2_TIM9 (1 << 2)
#define STM32_RCC_PB2_TIM10 (1 << 3)
#define STM32_RCC_PB2_TIM11 (1 << 4)
#define STM32_SYSCFG_BASE 0x40010000
@@ -370,12 +373,22 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
#define STM32_RCC_CFGR2 REG32(STM32_RCC_BASE + 0x2c) /* STM32F100 */
#define STM32_RCC_HB_DMA1 (1 << 0)
#define STM32_RCC_PB2_TIM1 (1 << 11)
#else
#error Unsupported chip variant
#endif
/* Peripheral bits for RCC_APB/AHB regs */
/* Peripheral bits for RCC_APB/AHB and DBGMCU regs */
#define STM32_RCC_PB1_TIM2 (1 << 0)
#define STM32_RCC_PB1_TIM3 (1 << 1)
#define STM32_RCC_PB1_TIM4 (1 << 2)
#define STM32_RCC_PB1_TIM5 (1 << 3)
#define STM32_RCC_PB1_TIM6 (1 << 4)
#define STM32_RCC_PB1_TIM7 (1 << 5)
#define STM32_RCC_PB1_RTC (1 << 10) /* DBGMCU only */
#define STM32_RCC_PB1_WWDG (1 << 11)
#define STM32_RCC_PB1_IWDG (1 << 12) /* DBGMCU only */
#define STM32_RCC_PB1_USART2 (1 << 17)
#define STM32_RCC_PB1_USART3 (1 << 18)
#define STM32_RCC_PB1_USART4 (1 << 19)