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https://github.com/Telecominfraproject/OpenCellular.git
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Set BOOTCFG register to test value
Needed for testing preprogramming chips Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8769 TEST=manual hibernate 1; should reboot rw 0x400fe1d0; should print: read word 0x400fe1d0 = 0xfffffdfe Change-Id: I95b419d7285a0bf5204f95d1f68f64dc212bb39e
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@@ -132,6 +132,10 @@ enum temp_sensor_id {
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#define TMP006_COUNT 1
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/* Target value for BOOTCFG. This currently toggles the polarity bit without
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* enabling the boot loader, simply to prove we can program it. */
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#define BOOTCFG_VALUE 0xfffffdfe
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void configure_board(void);
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#endif /* __BOARD_H */
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@@ -206,6 +206,16 @@ enum temp_sensor_id {
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/* The number of TMP006 sensor chips on the board. */
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#define TMP006_COUNT 4
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/* Target value for BOOTCFG. This currently toggles the polarity bit without
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* enabling the boot loader, simply to prove we can program it. */
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/* TODO: (crosbug.com/p/8769) set BOOTCFG to 0x7ffffffe, which will prevent
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* subsequent writes to BOOTCFG. Alternately, we could set BOOTCFG to some
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* signal which has a pullup/pulldown, and use that as a failsafe to get into
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* the boot loader, if we somehow brick the RO firmware. */
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#define BOOTCFG_VALUE 0xfffffdfe
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void configure_board(void);
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#endif /* __BOARD_H */
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@@ -211,6 +211,7 @@ static inline int lm4_fan_addr(int ch, int offset)
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#define LM4_SYSTEM_PIOSCCAL LM4REG(0x400fe150)
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#define LM4_SYSTEM_PIOSCSTAT LM4REG(0x400fe154)
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#define LM4_SYSTEM_PLLSTAT LM4REG(0x400fe168)
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#define LM4_SYSTEM_BOOTCFG LM4REG(0x400fe1d0)
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/* Note: USER_REG3 is used to hold pre-programming process data and should not
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* be modified by EC code. See crosbug.com/p/8889. */
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#define LM4_SYSTEM_USER_REG3 LM4REG(0x400fe1ec)
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@@ -5,6 +5,7 @@
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/* System module for Chrome EC : hardware specific implementation */
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#include "board.h"
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#include "cpu.h"
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#include "registers.h"
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#include "system.h"
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@@ -121,7 +122,9 @@ int system_pre_init(void)
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break;
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}
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}
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/* initialize properly registers after reset (cf errata) */
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/* Initialize registers after reset (cf errata) */
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/* TODO: fixed in A3 chip stepping? */
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wait_for_hibctl_wc();
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LM4_HIBERNATE_HIBRTCT = 0x7fff;
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wait_for_hibctl_wc();
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@@ -129,6 +132,15 @@ int system_pre_init(void)
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check_reset_cause();
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/* Initialize bootcfg if needed */
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if (LM4_SYSTEM_BOOTCFG != BOOTCFG_VALUE) {
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LM4_FLASH_FMD = BOOTCFG_VALUE;
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LM4_FLASH_FMA = 0x75100000;
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LM4_FLASH_FMC = 0xa4420008; /* WRKEY | COMT */
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while (LM4_FLASH_FMC & 0x08)
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;
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}
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return EC_SUCCESS;
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}
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