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npcx: shi: fix bug of clearing EVSTAT_EOR bit

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It is not proper to use SET_BIT macro to clear a "write 1 to clear" bit
in a register. It will also clear other bits if they are also set.

BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; boot up on gru, run ectool stress test for a while
without problem.

Change-Id: I0c5a850e85e41820515b1a8f15bb43d77397737f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/425589
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
CHLin
2017-01-09 14:55:20 +08:00
committed by chrome-bot
parent 690ab41d89
commit 52d333662a
1 changed files with 1 additions and 1 deletions
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2
chip/npcx/shi.c
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@@ -687,7 +687,7 @@ void shi_cs_event(enum gpio_signal signal)
* Clear possible EOR event from previous transaction since it's
* irrelevant now that CS is re-asserted.
*/
SET_BIT(NPCX_EVSTAT, NPCX_EVSTAT_EOR);
NPCX_EVSTAT = 1 << NPCX_EVSTAT_EOR;
/*
* Enable SHI interrupt - we will either succeed to parse our host