Add board support for Plankton

Board support for Planton, the Raiden testing board for type-C functional testing. BUG=none BRANCH=none TEST=make BOARD=plankton, load onto a plankton, and verify buttons are read correctly, and connect raiden to samus and verify that PD communication is successful Change-Id: I40922d5627d62f7f3540ac6a307596428d40baf5 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/207724
2025-12-28 02:35:28 +00:00 · 2014-07-13 17:42:32 -07:00
parent 3ac281f270
commit 537432085a
8 changed files with 573 additions and 1 deletions
--- a/board/plankton/board.c
+++ b/board/plankton/board.c
@@ -0,0 +1,110 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Plankton board configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "usb_pd.h"
+#include "usb_pd_config.h"
+#include "util.h"
+
+/* Debounce time for voltage buttons */
+#define BUTTON_DEBOUNCE_US (100 * MSEC)
+
+static enum gpio_signal button_pressed;
+
+/* Handle debounced button press */
+static void button_deferred(void)
+{
+	/* don't do anything if not in debug mode */
+	if (!gpio_get_level(GPIO_DBG_MODE_EN))
+		return;
+
+	/* bounce ? */
+	if (gpio_get_level(button_pressed) != 0)
+		return;
+
+	switch (button_pressed) {
+	case GPIO_DBG_5V_TO_DUT_L:
+	case GPIO_DBG_12V_TO_DUT_L:
+		pd_set_dual_role(PD_DRP_FORCE_SOURCE);
+		break;
+	case GPIO_DBG_CHG_TO_DEV_L:
+		pd_set_dual_role(PD_DRP_FORCE_SINK);
+		break;
+
+	case GPIO_DBG_USB_EN_L:
+		gpio_set_level(GPIO_USBC_SS_USB_MODE, 1);
+		break;
+	case GPIO_DBG_DP_EN_L:
+		gpio_set_level(GPIO_USBC_SS_USB_MODE, 0);
+		break;
+
+	case GPIO_DBG_CABLE_FLIP_L:
+		gpio_set_level(GPIO_USBC_DP_POLARITY,
+				!gpio_get_level(GPIO_USBC_DP_POLARITY));
+		break;
+	default:
+		break;
+	}
+
+	ccprintf("Button %d = %d\n",
+		 button_pressed, gpio_get_level(button_pressed));
+}
+DECLARE_DEFERRED(button_deferred);
+
+void button_event(enum gpio_signal signal)
+{
+	button_pressed = signal;
+	/* reset debounce time */
+	hook_call_deferred(button_deferred, BUTTON_DEBOUNCE_US);
+}
+
+void vbus_event(enum gpio_signal signal)
+{
+	ccprintf("VBUS! =%d\n", gpio_get_level(signal));
+	task_wake(TASK_ID_PD);
+}
+
+#include "gpio_list.h"
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+	[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"slave",  I2C_PORT_SLAVE, 100,
+		GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+static void board_init(void)
+{
+	/* Enable interrupts on VBUS transitions. */
+	gpio_enable_interrupt(GPIO_VBUS_WAKE);
+
+	/* Enable button interrupts. */
+	gpio_enable_interrupt(GPIO_DBG_12V_TO_DUT_L);
+	gpio_enable_interrupt(GPIO_DBG_CHG_TO_DEV_L);
+	gpio_enable_interrupt(GPIO_DBG_5V_TO_DUT_L);
+	gpio_enable_interrupt(GPIO_DBG_USB_EN_L);
+	gpio_enable_interrupt(GPIO_DBG_DP_EN_L);
+	gpio_enable_interrupt(GPIO_DBG_STATUS_CLEAR_L);
+	gpio_enable_interrupt(GPIO_DBG_CABLE_FLIP_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
--- a/board/plankton/board.h
+++ b/board/plankton/board.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Plankton board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART2 (PA14/PA15) */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 2
+
+/* Optional features */
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_INTERNAL_COMP
+#define CONFIG_ADC
+#define CONFIG_HW_CRC
+#define CONFIG_I2C
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TASK_PROFILING
+
+/* I2C ports configuration */
+#define I2C_PORT_SLAVE  0
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC     3
+
+#include "gpio_signal.h"
+
+/* ADC signal */
+enum adc_channel {
+	ADC_CH_CC1_PD = 0,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
--- a/board/plankton/build.mk
+++ b/board/plankton/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F072CBU6
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f07x
+
+board-y=board.o
+board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
--- a/board/plankton/ec.tasklist
+++ b/board/plankton/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD, pd_task, NULL, TASK_STACK_SIZE)
--- a/board/plankton/gpio.inc
+++ b/board/plankton/gpio.inc
@@ -0,0 +1,78 @@
+/* -*- mode:c -*-
+ *
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Inputs with interrupt handlers are first for efficiency */
+GPIO(VBUS_WAKE,         B, 5,  GPIO_INT_BOTH,    vbus_event)
+GPIO(DBG_12V_TO_DUT_L,  A, 4,  GPIO_INT_FALLING, button_event)
+GPIO(DBG_CHG_TO_DEV_L,  A, 7,  GPIO_INT_FALLING, button_event)
+GPIO(DBG_5V_TO_DUT_L,   B, 8,  GPIO_INT_FALLING, button_event)
+GPIO(DBG_MODE_EN,       B, 10, GPIO_INT_BOTH,    button_event)
+GPIO(DBG_USB_EN_L,      B, 11, GPIO_INT_FALLING, button_event)
+GPIO(DBG_DP_EN_L,       B, 12, GPIO_INT_FALLING, button_event)
+GPIO(DBG_STATUS_CLEAR_L,C, 13, GPIO_INT_FALLING, button_event)
+GPIO(DBG_CABLE_FLIP_L,  B, 15, GPIO_INT_FALLING, button_event)
+
+/* PD RX/TX */
+GPIO(USBC_PD_REF,       A, 0,  GPIO_ANALOG,   NULL)
+GPIO(USBC_CC1_PD,       A, 1,  GPIO_ANALOG,   NULL)
+GPIO(USBC_CC_TX_EN,     A, 3,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_CC_TX_DATA,   A, 6,  GPIO_OUT_LOW,  NULL)
+
+#if 0
+/* Alternate functions */
+GPIO(USBC_TX_CLKOUT,    B, 9,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_TX_CLKIN,     A, 5,  GPIO_OUT_LOW,  NULL)
+#endif
+
+/* USB-C Power and muxes control */
+GPIO(USBC_CHARGE_EN,    A, 8,  GPIO_OUT_HIGH, NULL)
+GPIO(USBC_CC_DEVICE_ODL,A, 9,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_CC_HOST,      A, 2,  GPIO_INPUT,    NULL)
+GPIO(USBC_5V_EN,        A, 10, GPIO_OUT_LOW,  NULL)
+GPIO(USBC_12V_EN,       C, 14, GPIO_OUT_LOW,  NULL)
+GPIO(USBC_DP_MODE_L,    B, 0,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_DP_POLARITY,  B, 1,  GPIO_OUT_HIGH, NULL)
+GPIO(USBC_SS_USB_MODE,  B, 3,  GPIO_OUT_LOW,  NULL)
+GPIO(USBC_SS_EN_L,      B, 4,  GPIO_OUT_LOW,  NULL)
+
+/* Alternate functions */
+#if 0
+GPIO(USB_DM,            A, 11, GPIO_ANALOG,   NULL)
+GPIO(USB_DP,            A, 12, GPIO_ANALOG,   NULL)
+GPIO(UART_TX,           A, 14, GPIO_OUT_LOW,  NULL)
+GPIO(UART_RX,           A, 15, GPIO_OUT_LOW,  NULL)
+#endif
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SLAVE_I2C_SCL,     B, 6,  GPIO_INPUT,    NULL)
+GPIO(SLAVE_I2C_SDA,     B, 7,  GPIO_INPUT,    NULL)
+
+/* Outputs */
+GPIO(SLAVE_I2C_INT_L,   B, 2,  GPIO_OUT_HIGH, NULL)
+GPIO(RAIDEN_CC1_EN_L,   B, 13, GPIO_OUT_LOW,  NULL)
+GPIO(RAIDEN_CC2_EN_L,   B, 14, GPIO_OUT_HIGH, NULL)
+
+/* Inputs */
+GPIO(SLOT_PLN_A0,       C, 15, GPIO_INPUT,    NULL)
+GPIO(SLOT_PLN_A1,       F, 0,  GPIO_INPUT,    NULL)
+GPIO(SLOT_PLN_A2,       F, 1,  GPIO_INPUT,    NULL)
+
+/* Test points */
+GPIO(TP9,               A, 13, GPIO_ODR_HIGH, NULL)
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+ALTERNATE(A, 0x0020, 0, MODULE_USB_PD, 0) /* SPI1: SCK(PA5) */
+ALTERNATE(B, 0x0200, 2, MODULE_USB_PD, 0) /* TIM17_CH1: (PB9) */
+ALTERNATE(A, 0xC000, 1, MODULE_UART,   0) /* USART2: PA14/PA15 */
+ALTERNATE(B, 0x00C0, 1, MODULE_I2C,    0) /* I2C SLAVE:PB6/7 */
+
--- a/board/plankton/usb_pd_config.h
+++ b/board/plankton/usb_pd_config.h
@@ -0,0 +1,164 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USB Power delivery board configuration */
+
+#ifndef __USB_PD_CONFIG_H
+#define __USB_PD_CONFIG_H
+
+/* USB-PD configuration */
+#define PD_PORT_COUNT 1
+#define PORT_TO_TASK_ID(port) TASK_ID_PD
+#define TASK_ID_TO_PORT(id)   0
+
+/* Timer selection for baseband PD communication */
+#define TIM_CLOCK_PD_TX_C0 17
+#define TIM_CLOCK_PD_RX_C0 1
+
+#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
+#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
+
+/* Timer channel */
+#define TIM_RX_CCR_C0 1
+
+/* RX timer capture/compare register */
+#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
+#define TIM_RX_CCR_REG(p) TIM_CCR_C0
+
+/* TX and RX timer register */
+#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
+#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
+#define TIM_REG_TX(p) TIM_REG_TX_C0
+#define TIM_REG_RX(p) TIM_REG_RX_C0
+
+/* use the hardware accelerator for CRC */
+#define CONFIG_HW_CRC
+
+/* TX is using SPI1 on PA4-7 */
+#define SPI_REGS(p) STM32_SPI1_REGS
+
+static inline void spi_enable_clock(int port)
+{
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
+}
+
+#define DMAC_SPI_TX(p) STM32_DMAC_CH3
+
+/* RX is using COMP1 triggering TIM1 CH1 */
+#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
+#define CMP2OUTSEL 0
+
+#define TIM_CCR_IDX(p) TIM_RX_CCR_C0
+#define TIM_CCR_CS  1
+#define EXTI_COMP_MASK(p) (1 << 21)
+#define IRQ_COMP STM32_IRQ_COMP
+/* triggers packet detection on comparator falling edge */
+#define EXTI_XTSR STM32_EXTI_FTSR
+
+#define DMAC_TIM_RX(p) STM32_DMAC_CH2
+
+/* the pins used for communication need to be hi-speed */
+static inline void pd_set_pins_speed(int port)
+{
+	/* 40 MHz pin speed on SPI1 PA5/6 */
+	STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00003C00;
+	/* 40 MHz pin speed on TIM17_CH1 (PB9) */
+	STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C0000;
+}
+
+/* Reset SPI peripheral used for TX */
+static inline void pd_tx_spi_reset(int port)
+{
+	/* Reset SPI1 */
+	STM32_RCC_APB2RSTR |= (1 << 12);
+	STM32_RCC_APB2RSTR &= ~(1 << 12);
+}
+
+/* Drive the CC line from the TX block */
+static inline void pd_tx_enable(int port, int polarity)
+{
+	/* put SPI function on TX pin */
+	/* PA6 is SPI1 MISO */
+	gpio_set_alternate_function(GPIO_A, 0x0040, 0);
+
+	/* set the low level reference */
+	gpio_set_level(GPIO_USBC_CC_TX_EN, 1);
+}
+
+/* Put the TX driver in Hi-Z state */
+static inline void pd_tx_disable(int port, int polarity)
+{
+	/* output low on SPI TX to disable the FET */
+	/* PA6 is SPI1_MISO */
+	STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
+				   & ~(3 << (2*6)))
+				   |  (1 << (2*6));
+	/* put the low level reference in Hi-Z */
+	gpio_set_level(GPIO_USBC_CC_TX_EN, 0);
+}
+
+/* we know the plug polarity, do the right configuration */
+static inline void pd_select_polarity(int port, int polarity)
+{
+	/* use the right comparator non inverted input for COMP1 */
+	STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
+			| STM32_COMP_CMP1EN
+			| STM32_COMP_CMP1INSEL_INM6;
+}
+
+/* Initialize pins used for TX and put them in Hi-Z */
+static inline void pd_tx_init(void)
+{
+	/* Configure SCK pin */
+	gpio_config_module(MODULE_USB_PD, 1);
+}
+
+static inline void pd_set_host_mode(int port, int enable)
+{
+	ccprintf("Host mode: %d\n", enable);
+	if (enable) {
+		/* Source mode, disable charging */
+		gpio_set_level(GPIO_USBC_CHARGE_EN, 0);
+		/* High Z for no pull-down resistor on CC */
+		gpio_set_flags_by_mask(GPIO_A, (1 << 9), GPIO_INPUT);
+		/* Set pull-up resistor on CC */
+		gpio_set_flags_by_mask(GPIO_A, (1 << 2), GPIO_OUT_HIGH);
+	} else {
+		/* Device mode, disable VBUS */
+		gpio_set_level(GPIO_USBC_5V_EN, 0);
+		gpio_set_level(GPIO_USBC_12V_EN, 0);
+		/* High Z for no pull-up resistor on CC */
+		gpio_set_flags_by_mask(GPIO_A, (1 << 2), GPIO_INPUT);
+		/* Set pull-down resistor on CC. */
+		gpio_set_flags_by_mask(GPIO_A, (1 << 9), GPIO_OUT_LOW);
+		/* Set charge enable */
+		gpio_set_level(GPIO_USBC_CHARGE_EN, 1);
+	}
+}
+
+static inline int pd_adc_read(int port, int cc)
+{
+	/* Always return CC1 */
+	return adc_read_channel(ADC_CH_CC1_PD);
+}
+
+static inline int pd_snk_is_vbus_provided(int port)
+{
+	return gpio_get_level(GPIO_VBUS_WAKE);
+}
+
+/* 3.0A DFP : no-connect voltage is 2.45V */
+#define PD_SRC_VNC 2450 /* mV */
+
+/* UFP-side : threshold for DFP connection detection */
+#define PD_SNK_VA   250 /* mV */
+
+/* we are acting only as a sink */
+#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
+
+/* delay necessary for the voltage transition on the power supply */
+#define PD_POWER_SUPPLY_TRANSITION_DELAY 50000 /* us */
+
+#endif /* __USB_PD_CONFIG_H */
--- a/board/plankton/usb_pd_policy.c
+++ b/board/plankton/usb_pd_policy.c
@@ -0,0 +1,127 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "adc.h"
+#include "board.h"
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+#include "usb_pd.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+/* Acceptable margin between requested VBUS and measured value */
+#define MARGIN_MV 400 /* mV */
+
+/* we are not acting as a source */
+const uint32_t pd_src_pdo[] = {
+		PDO_FIXED(5000,   500, PDO_FIXED_EXTERNAL),
+		PDO_FIXED(12000, 3000, PDO_FIXED_EXTERNAL),
+};
+const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
+
+/* Fake PDOs : we just want our pre-defined voltages */
+const uint32_t pd_snk_pdo[] = {
+		PDO_FIXED(5000,   500, 0),
+		PDO_FIXED(12000,  500, 0),
+		PDO_FIXED(20000,  500, 0),
+};
+const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
+
+/* Desired voltage requested as a sink (in millivolts) */
+static unsigned select_mv = 5000;
+
+int pd_choose_voltage(int cnt, uint32_t *src_caps, uint32_t *rdo)
+{
+	int i;
+	int ma;
+	int set_mv = select_mv;
+
+	/* Default to 5V */
+	if (set_mv <= 0)
+		set_mv = 5000;
+
+	/* Get the selected voltage */
+	for (i = cnt; i >= 0; i--) {
+		int mv = ((src_caps[i] >> 10) & 0x3FF) * 50;
+		int type = src_caps[i] & PDO_TYPE_MASK;
+		if ((mv == set_mv) && (type == PDO_TYPE_FIXED))
+			break;
+	}
+	if (i < 0)
+		return -EC_ERROR_UNKNOWN;
+
+	/* request all the power ... */
+	ma = 10 * (src_caps[i] & 0x3FF);
+	*rdo = RDO_FIXED(i + 1, ma, ma, 0);
+	ccprintf("Request [%d] %d V %d mA\n", i, set_mv/1000, ma);
+	return EC_SUCCESS;
+}
+
+void pd_set_max_voltage(unsigned mv)
+{
+	select_mv = mv;
+}
+
+int requested_voltage_idx;
+int pd_request_voltage(uint32_t rdo)
+{
+	int op_ma = rdo & 0x3FF;
+	int max_ma = (rdo >> 10) & 0x3FF;
+	int idx = rdo >> 28;
+	uint32_t pdo;
+	uint32_t pdo_ma;
+
+	if (!idx || idx > pd_src_pdo_cnt)
+		return EC_ERROR_INVAL; /* Invalid index */
+
+	/* check current ... */
+	pdo = pd_src_pdo[idx - 1];
+	pdo_ma = (pdo & 0x3ff);
+	if (op_ma > pdo_ma)
+		return EC_ERROR_INVAL; /* too much op current */
+	if (max_ma > pdo_ma)
+		return EC_ERROR_INVAL; /* too much max current */
+
+	ccprintf("Switch to %d V %d mA (for %d/%d mA)\n",
+		 ((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
+		 ((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10);
+
+	requested_voltage_idx = idx;
+
+	return EC_SUCCESS;
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Output the correct voltage */
+	gpio_set_level(requested_voltage_idx ? GPIO_USBC_12V_EN :
+					       GPIO_USBC_5V_EN, 1);
+
+	return EC_SUCCESS;
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Kill VBUS */
+	requested_voltage_idx = 0;
+	gpio_set_level(GPIO_USBC_5V_EN, 0);
+	gpio_set_level(GPIO_USBC_12V_EN, 0);
+}
+
+int pd_board_checks(void)
+{
+	return EC_SUCCESS;
+}
+
+int pd_power_negotiation_allowed(void)
+{
+	return 1;
+}
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -295,7 +295,8 @@ save="$(servo_save)"

 case "${BOARD}" in
 	big | discovery | nyan | pit | snow | spring | veyron ) flash_stm32 ;;
-	fruitpie | zinger | firefly | samus_pd | ryu | ryu_sh) flash_stm32 ;;
+	fruitpie | zinger | firefly | samus_pd | ryu | ryu_sh ) flash_stm32 ;;
+	plankton ) flash_stm32 ;;
 	twinkie) flash_stm32_dfu ;;
 	falco | peppy | rambi | samus | squawks ) flash_lm4 ;;
 	link ) flash_link ;;