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cleanup: lars / kunimitsu (and _pd): Remove board-level code

Browse Source 
Authoritative firmware for these boards can be found on
firmware-glados-7820.B branch.

BUG=chrome-os-partner:49909
BRANCH=None
TEST=`make buildall -j`

Change-Id: I78dddef7bc36ecceb5cd9f0eb07052e8e16b6c15
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343201
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2016-05-06 16:14:33 -07:00
committed by chrome-bot
parent f36943f95a
commit 541433abaf
30 changed files with 1 additions and 4044 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
board/kunimitsu/Makefile
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../../Makefile

83
board/kunimitsu/battery.c
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "adc.h"
#include "battery.h"
#include "battery_smart.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define SB_SHUTDOWN_DATA 0x0010
static const struct battery_info info = {
.voltage_max = 8700,/* mV */
.voltage_normal = 7600,
.voltage_min = 6100,
.precharge_current = 150,/* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 45,
.charging_min_c = 0,
.charging_max_c = 45,
.discharging_min_c = -20,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
int rv;
/* Ship mode command must be sent twice to take effect */
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
if (rv != EC_SUCCESS)
return rv;
return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
}
#ifdef CONFIG_BATTERY_PRESENT_CUSTOM
/*
* Physical detection of battery via ADC.
*
* Upper limit of valid voltage level (mV), when battery is attached to ADC
* port, is across the internal thermistor with external pullup resistor.
*/
#define BATT_PRESENT_MV 1500
enum battery_present battery_is_present(void)
{
enum battery_present batt_pres;
int batt_status;
/*
* if voltage is below certain level (dependent on ratio of
* internal thermistor and external pullup resister),
* battery is attached.
*/
batt_pres = (adc_read_channel(ADC_BATT_PRESENT) > BATT_PRESENT_MV) ?
BP_NO : BP_YES;
/*
* Make sure battery status is implemented, I2C transactions are
* success & the battery status is Initialized to find out if it
* is a working battery and it is not in the cut-off mode.
*
* FETs are turned off after Power Shutdown time.
* The device will wake up when a voltage is applied to PACK.
* Battery status will be inactive until it is initialized.
*/
if (batt_pres == BP_YES && !battery_status(&batt_status))
if (!(batt_status & STATUS_INITIALIZED))
batt_pres = BP_NO;
return batt_pres;
}
#endif

658
board/kunimitsu/board.c
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@@ -1,658 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Skylake Chrome Reference Design board-specific configuration */
#include "adc.h"
#include "adc_chip.h"
#include "als.h"
#include "battery.h"
#include "button.h"
#include "charge_manager.h"
#include "charge_state.h"
#include "charger.h"
#include "console.h"
#include "driver/accel_kionix.h"
#include "driver/accel_kxcj9.h"
#include "driver/als_opt3001.h"
#include "driver/gyro_l3gd20h.h"
#include "driver/pmic_tps650830.h"
#include "driver/tcpm/tcpci.h"
#include "driver/temp_sensor/tmp432.h"
#include "extpower.h"
#include "fan.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "i2c.h"
#include "lid_switch.h"
#include "math_util.h"
#include "motion_lid.h"
#include "motion_sense.h"
#include "pi3usb9281.h"
#include "power.h"
#include "power_button.h"
#include "spi.h"
#include "switch.h"
#include "system.h"
#include "task.h"
#include "temp_sensor.h"
#include "temp_sensor_chip.h"
#include "thermal.h"
#include "timer.h"
#include "uart.h"
#include "usb_charge.h"
#include "usb_mux.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "util.h"
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
#define TPS650830_I2C_ADDR TPS650830_I2C_ADDR1
/* Exchange status with PD MCU. */
static void pd_mcu_interrupt(enum gpio_signal signal)
{
#ifdef HAS_TASK_PDCMD
/* Exchange status with PD MCU to determine interrupt cause */
host_command_pd_send_status(0);
#endif
}
void vbus0_evt(enum gpio_signal signal)
{
/* VBUS present GPIO is inverted */
usb_charger_vbus_change(0, !gpio_get_level(signal));
task_wake(TASK_ID_PD_C0);
}
void vbus1_evt(enum gpio_signal signal)
{
/* VBUS present GPIO is inverted */
usb_charger_vbus_change(1, !gpio_get_level(signal));
task_wake(TASK_ID_PD_C1);
}
void usb0_evt(enum gpio_signal signal)
{
task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
}
void usb1_evt(enum gpio_signal signal)
{
task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12, 0);
}
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_RSMRST_L_PGOOD, 1, "RSMRST_N_PWRGD"},
{GPIO_PCH_SLP_S0_L, 1, "SLP_S0_DEASSERTED"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"},
{GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"},
{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS_DEASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* VBUS_MUL */
#define VBUS_MUL 30123
/* VBUS_DIV 10bit ADC */
#define VBUS_DIV 1024
/* VBUS_SHIFT */
#define VBUS_SHIFT 116
/* ADC channels */
const struct adc_t adc_channels[] = {
/* read voltage in battery thermistor as battery present */
[ADC_BATT_PRESENT] = {"BATTPRES", 3300, 1024, 0, 0},
/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
[ADC_VBUS] = {"VBUS", VBUS_MUL, VBUS_DIV, VBUS_SHIFT, 1},
/* Adapter current output or battery discharging current */
[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
/*
* System current consumption. Converted to mV,
* full ADC is equivalent to 100W
*/
[ADC_PSYS] = {"PSYS", 3000, 1024, 0, 4},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
const struct i2c_port_t i2c_ports[] = {
{"pmic", MEC1322_I2C0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
{"muxes", MEC1322_I2C0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
{"pd_mcu", MEC1322_I2C1, 500, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
{"sensors", MEC1322_I2C2, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA },
{"batt", MEC1322_I2C3, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA },
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = {
{I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR, &tcpci_tcpm_drv},
{I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR + 2, &tcpci_tcpm_drv},
};
/* Physical fans. These are logically separate from pwm_channels. */
const struct fan_t fans[] = {
{.flags = FAN_USE_RPM_MODE,
.rpm_min = 1000,
.rpm_start = 1000,
.rpm_max = 5200,
.ch = 1,
.pgood_gpio = -1,
.enable_gpio = GPIO_FAN_PWR_DIS_L,
},
};
BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
/* SPI devices */
const struct spi_device_t spi_devices[] = {
{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
const enum gpio_signal hibernate_wake_pins[] = {
GPIO_AC_PRESENT,
GPIO_LID_OPEN,
GPIO_POWER_BUTTON_L,
};
const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
struct pi3usb9281_config pi3usb9281_chips[] = {
{
.i2c_port = I2C_PORT_USB_CHARGER_1,
.mux_lock = NULL,
},
{
.i2c_port = I2C_PORT_USB_CHARGER_2,
.mux_lock = NULL,
},
};
BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT);
struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = {
{
.port_addr = 0xa8,
.driver = &pi3usb30532_usb_mux_driver,
},
{
.port_addr = 0xaa,
.driver = &pi3usb30532_usb_mux_driver,
}
};
/**
* Reset PD MCU
*/
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_PD_RST_L, 0);
usleep(100);
gpio_set_level(GPIO_PD_RST_L, 1);
}
#ifdef HAS_TASK_MOTIONSENSE
/* Four Motion sensors */
/* kxcj9 mutex and local/private data*/
static struct mutex g_kxcj9_mutex[2];
struct kionix_accel_data g_kxcj9_data[2] = {
{.variant = KXCJ9},
{.variant = KXCJ9},
};
#ifdef CONFIG_GYRO_L3GD20H
/* Gyro sensor */
/* l3gd20h mutex and local/private data*/
static struct mutex g_l3gd20h_mutex;
struct l3gd20_data g_l3gd20h_data;
#endif
/* Matrix to rotate accelrator into standard reference frame */
const matrix_3x3_t base_standard_ref = {
{ 0, FLOAT_TO_FP(-1), 0},
{FLOAT_TO_FP(-1), 0, 0},
{ 0, 0, FLOAT_TO_FP(-1)}
};
const matrix_3x3_t lid_standard_ref = {
{FLOAT_TO_FP(-1), 0, 0},
{ 0, FLOAT_TO_FP(1), 0},
{ 0, 0, FLOAT_TO_FP(-1)}
};
struct motion_sensor_t motion_sensors[] = {
{.name = "Base Accel",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_KXCJ9,
.type = MOTIONSENSE_TYPE_ACCEL,
.location = MOTIONSENSE_LOC_BASE,
.drv = &kionix_accel_drv,
.mutex = &g_kxcj9_mutex[0],
.drv_data = &g_kxcj9_data[0],
.port = I2C_PORT_ACCEL,
.addr = KXCJ9_ADDR1,
.rot_standard_ref = &base_standard_ref,
.default_range = 2, /* g, enough for laptop. */
.config = {
/* AP: by default shutdown all sensors */
[SENSOR_CONFIG_AP] = {
.odr = 0,
.ec_rate = 0,
},
/* EC use accel for angle detection */
[SENSOR_CONFIG_EC_S0] = {
.odr = 100000 | ROUND_UP_FLAG,
.ec_rate = 100 * MSEC,
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S3] = {
.odr = 0,
.ec_rate = 0
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S5] = {
.odr = 0,
.ec_rate = 0
},
},
},
{.name = "Lid Accel",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_KXCJ9,
.type = MOTIONSENSE_TYPE_ACCEL,
.location = MOTIONSENSE_LOC_LID,
.drv = &kionix_accel_drv,
.mutex = &g_kxcj9_mutex[1],
.drv_data = &g_kxcj9_data[1],
.port = I2C_PORT_ACCEL,
.addr = KXCJ9_ADDR0,
.rot_standard_ref = &lid_standard_ref,
.default_range = 2, /* g, enough for laptop. */
.config = {
/* AP: by default shutdown all sensors */
[SENSOR_CONFIG_AP] = {
.odr = 0,
.ec_rate = 0,
},
/* EC use accel for angle detection */
[SENSOR_CONFIG_EC_S0] = {
.odr = 100000 | ROUND_UP_FLAG,
.ec_rate = 100 * MSEC,
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S3] = {
.odr = 0,
.ec_rate = 0
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S5] = {
.odr = 0,
.ec_rate = 0
},
},
},
#ifdef CONFIG_GYRO_L3GD20H
{.name = "Lid Gyro",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_L3GD20H,
.type = MOTIONSENSE_TYPE_GYRO,
.location = MOTIONSENSE_LOC_LID,
.drv = &l3gd20h_drv,
.mutex = &g_l3gd20h_mutex,
.drv_data = &g_l3gd20h_data,
.port = I2C_PORT_GYRO,
.addr = L3GD20_ADDR1,
.rot_standard_ref = NULL,
.default_range = 2000, /* DPS */
.config = {
/* AP: by default shutdown all sensors */
[SENSOR_CONFIG_AP] = {
.odr = 0,
.ec_rate = 0,
},
[SENSOR_CONFIG_EC_S0] = {
.odr = 0,
.ec_rate = 0,
},
/* unused */
[SENSOR_CONFIG_EC_S3] = {
.odr = 0,
.ec_rate = 0,
},
[SENSOR_CONFIG_EC_S5] = {
.odr = 0,
.ec_rate = 0,
},
},
},
#endif
};
const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
#endif
/*
* Temperature sensors data; must be in same order as enum temp_sensor_id.
* Sensor index and name must match those present in coreboot:
* src/mainboard/google/${board}/acpi/dptf.asl
*/
const struct temp_sensor_t temp_sensors[] = {
{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_LOCAL, 4},
{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_REMOTE1, 4},
{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_REMOTE2, 4},
{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_temp_sensor_get_val,
0, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/*
* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
* same order as enum temp_sensor_id. To always ignore any temp, use 0.
*/
struct ec_thermal_config thermal_params[] = {
/* {Twarn, Thigh, Thalt}, fan_off, fan_max */
{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
{{0, 0, 0}, 0, 0}, /* Battery */
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
/* ALS instances. Must be in same order as enum als_id. */
struct als_t als[] = {
{"TI", opt3001_init, opt3001_read_lux, 5},
};
BUILD_ASSERT(ARRAY_SIZE(als) == ALS_COUNT);
const struct button_config buttons[CONFIG_BUTTON_COUNT] = {
{"Volume Down", KEYBOARD_BUTTON_VOLUME_DOWN, GPIO_VOLUME_DOWN_L,
30 * MSEC, 0},
{"Volume Up", KEYBOARD_BUTTON_VOLUME_UP, GPIO_VOLUME_UP_L,
30 * MSEC, 0},
};
BUILD_ASSERT(ARRAY_SIZE(buttons) == CONFIG_BUTTON_COUNT);
/* Initialize PMIC */
#define I2C_PMIC_READ(reg, data) \
i2c_read8(I2C_PORT_PMIC, TPS650830_I2C_ADDR, (reg), (data))
#define I2C_PMIC_WRITE(reg, data) \
i2c_write8(I2C_PORT_PMIC, TPS650830_I2C_ADDR, (reg), (data))
static void board_pmic_init(void)
{
int ret;
int data;
int error_count = 0;
/* No need to re-init PMIC since settings are sticky across sysjump */
if (system_jumped_to_this_image())
return;
/* Read vendor ID */
while (1) {
ret = I2C_PMIC_READ(TPS650830_REG_VENDORID, &data);
if (!ret && data == TPS650830_VENDOR_ID) {
break;
} else if (error_count > 5)
goto pmic_error;
error_count++;
}
/*
* VCCIOCNT register setting
* [6] : CSDECAYEN
* otherbits: default
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_VCCIOCNT, 0x4A);
if (ret)
goto pmic_error;
/*
* VRMODECTRL:
* [4] : VCCIOLPM clear
* otherbits: default
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_VRMODECTRL, 0x2F);
if (ret)
goto pmic_error;
/*
* PGMASK1 : Exclude VCCIO from Power Good Tree
* [7] : MVCCIOPG clear
* otherbits: default
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_PGMASK1, 0x80);
if (ret)
goto pmic_error;
/*
* PWFAULT_MASK1 Register settings
* [7] : 1b V4 Power Fault Masked
* [4] : 1b V7 Power Fault Masked
* [2] : 1b V9 Power Fault Masked
* [0] : 1b V13 Power Fault Masked
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_PWFAULT_MASK1, 0x95);
if (ret)
goto pmic_error;
/*
* Discharge control 4 register configuration
* [7:6] : 00b Reserved
* [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm
* [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm
* [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT4, 0x15);
if (ret)
goto pmic_error;
/*
* Discharge control 3 register configuration
* [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm
* [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm
* [3:2] : 01b V100A discharge resistance (V11), 100 Ohm
* [1:0] : 01b V085A discharge resistance (V12), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT3, 0x55);
if (ret)
goto pmic_error;
/*
* Discharge control 2 register configuration
* [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm
* [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm
* [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm
* [1:0] : 01b V18A discharge resistance (V8), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT2, 0x55);
if (ret)
goto pmic_error;
/*
* Discharge control 1 register configuration
* [7:2] : 00b Reserved
* [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT1, 0x01);
if (ret)
goto pmic_error;
/*
* Increase Voltage
* [7:0] : 0x2a default
* [5:4] : 10b default
* [5:4] : 01b 5.1V (0x1a)
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_V5ADS3CNT, 0x1a);
if (ret)
goto pmic_error;
/*
* PBCONFIG Register configuration
* [7] : 1b Power button debounce, 0ms (no debounce)
* [6] : 0b Power button reset timer logic, no action (default)
* [5:0] : 011111b Force an Emergency reset time, 31s (default)
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_PBCONFIG, 0x9F);
if (ret)
goto pmic_error;
CPRINTS("PMIC initialization done");
return;
pmic_error:
CPRINTS("PMIC initialization failed");
}
DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_INIT_I2C + 1);
/* Initialize board. */
static void board_init(void)
{
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
/* Enable pericom BC1.2 interrupts */
gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_L);
/* Provide AC status to the PCH */
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/**
* Buffer the AC present GPIO to the PCH.
*/
static void board_extpower(void)
{
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
/**
* Set active charge port -- only one port can be active at a time.
*
* @param charge_port Charge port to enable.
*
* Returns EC_SUCCESS if charge port is accepted and made active,
* EC_ERROR_* otherwise.
*/
int board_set_active_charge_port(int charge_port)
{
/* charge port is a realy physical port */
int is_real_port = (charge_port >= 0 &&
charge_port < CONFIG_USB_PD_PORT_COUNT);
/* check if we are source vbus on that port */
int source = gpio_get_level(charge_port == 0 ? GPIO_USB_C0_5V_EN :
GPIO_USB_C1_5V_EN);
if (is_real_port && source) {
CPRINTS("Skip enable p%d", charge_port);
return EC_ERROR_INVAL;
}
CPRINTS("New chg p%d", charge_port);
if (charge_port == CHARGE_PORT_NONE) {
/* Disable both ports */
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1);
} else {
/* Make sure non-charging port is disabled */
gpio_set_level(charge_port ? GPIO_USB_C0_CHARGE_EN_L :
GPIO_USB_C1_CHARGE_EN_L, 1);
/* Enable charging port */
gpio_set_level(charge_port ? GPIO_USB_C1_CHARGE_EN_L :
GPIO_USB_C0_CHARGE_EN_L, 0);
}
return EC_SUCCESS;
}
/**
* Set the charge limit based upon desired maximum.
*
* @param charge_ma Desired charge limit (mA).
*/
void board_set_charge_limit(int charge_ma)
{
charge_set_input_current_limit(MAX(charge_ma,
CONFIG_CHARGER_INPUT_CURRENT));
}
/* Enable touchpad on chipset startup so that it can wake the system */
static void board_chipset_startup(void)
{
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
}
DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
HOOK_PRIO_DEFAULT);
/* Disable touchpad on chipset shutdown as it is no longer useful */
static void board_chipset_shutdown(void)
{
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown,
HOOK_PRIO_DEFAULT);
/* Make the pmic re-sequence the power rails under these conditions. */
#define PMIC_RESET_FLAGS \
(RESET_FLAG_WATCHDOG | RESET_FLAG_SOFT | RESET_FLAG_HARD)
static void board_handle_reboot(void)
{
int flags;
if (system_jumped_to_this_image())
return;
/* Interrogate current reset flags from previous reboot. */
flags = system_get_reset_flags();
if (!(flags & PMIC_RESET_FLAGS))
return;
/* Preserve AP off request. */
if (flags & RESET_FLAG_AP_OFF)
chip_save_reset_flags(RESET_FLAG_AP_OFF);
ccprintf("Restarting system with PMIC.\n");
/* Flush console */
cflush();
/* Bring down all rails but RTC rail (including EC power). */
gpio_set_level(GPIO_LDO_EN, 1);
while (1)
; /* wait here */
}
DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
void board_hibernate(void)
{
CPRINTS("Enter Pseudo G3");
/*
* Clean up the UART buffer and prevent any unwanted garbage characters
* before power off and also ensure above debug message is printed.
*/
cflush();
gpio_set_level(GPIO_G3_SLEEP_EN, 1);
/* Power to EC should shut down now */
while (1)
;
}

233
board/kunimitsu/board.h
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Skylake Chrome Reference Design board configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/*
* Allow dangerous commands.
* TODO: Remove this config before production.
*/
#define CONFIG_SYSTEM_UNLOCKED
/* Optional features */
#define CONFIG_ADC
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_PRESENT_CUSTOM
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_VERSION
#define CONFIG_BUTTON_COUNT 2
#define CONFIG_CHARGE_MANAGER
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V2
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_ISL9237
#define CONFIG_CHARGER_ILIM_PIN_DISABLED
#define CONFIG_CHARGER_INPUT_CURRENT 512
#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 1
#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15000
#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
#define CONFIG_CHARGER_NARROW_VDC
#define CONFIG_CHARGER_PSYS
#define CONFIG_CHARGER_SENSE_RESISTOR 10
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
#define CONFIG_TRICKLE_CHARGING
#define CONFIG_REPLACE_LOADER_WITH_BSS_SLOW
/* PSYS resistor 8.25KOhm */
#define CHARGER_PSYS_RESISTOR 8250
/*
* PSYS gain = 1 / (PSYS resistor * (1.44 or 0.36) uA/W)
*/
#define ISL9237_C2_PSYS_GAIN_1_44 (100000000ul / (CHARGER_PSYS_RESISTOR * 144))
#define ISL9237_C2_PSYS_GAIN_0_36 (100000000ul / (CHARGER_PSYS_RESISTOR * 36))
#define CONFIG_CHIPSET_SKYLAKE
#define CONFIG_CHIPSET_RESET_HOOK
#define CONFIG_CLOCK_CRYSTAL
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FANS 1
#define CONFIG_HOSTCMD_PD
#define CONFIG_I2C
#define CONFIG_I2C_MASTER
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_COMMON
#define CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LTO
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
/* All data won't fit in data RAM. So, moving boundary slightly. */
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE (104 * 1024)
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* We're space constrained on Kunimitsu, so reduce the UART TX buffer size. */
#undef CONFIG_UART_TX_BUF_SIZE
#define CONFIG_UART_TX_BUF_SIZE 512
#define CONFIG_POWER_S0IX
#define CONFIG_USB_CHARGER
#define CONFIG_USB_MUX_PI3USB30532
#define CONFIG_USB_POWER_DELIVERY
#define CONFIG_USB_PD_ALT_MODE
#define CONFIG_USB_PD_ALT_MODE_DFP
#define CONFIG_USB_PD_COMM_LOCKED
#define CONFIG_USB_PD_CUSTOM_VDM
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_LOGGING
#define CONFIG_USB_PD_LOG_SIZE 128
#define CONFIG_USB_PD_PORT_COUNT 2
#define CONFIG_USB_PD_TCPM_TCPCI
#define CONFIG_USB_PD_TRY_SRC
#define CONFIG_USB_SWITCH_PI3USB9281
#define CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT 2
#define CONFIG_USBC_SS_MUX
#define CONFIG_USBC_SS_MUX_DFP_ONLY
#define CONFIG_USBC_VCONN
#define CONFIG_USBC_VCONN_SWAP
/* USB-A ports */
#define USB_PORT_COUNT 2
#define CONFIG_USB_PORT_POWER_DUMB
#define CONFIG_VBOOT_HASH
#define CONFIG_SPI_FLASH_PORT 1
#define CONFIG_SPI_FLASH
#define CONFIG_FLASH_SIZE 524288
#define CONFIG_SPI_FLASH_W25X40
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_TMP432
/*
* Enable 1 slot of secure temporary storage to support
* suspend/resume with read/write memory training.
*/
#define CONFIG_VSTORE
#define CONFIG_VSTORE_SLOT_COUNT 1
#define CONFIG_WATCHDOG_HELP
/* LED signals */
#define GPIO_BAT_LED_AMBER GPIO_CHARGE_LED1
#define GPIO_BAT_LED_BLUE GPIO_CHARGE_LED2
/* I2C ports */
#define I2C_PORT_BATTERY MEC1322_I2C3
#define I2C_PORT_CHARGER MEC1322_I2C3
#define I2C_PORT_THERMAL MEC1322_I2C3
#define I2C_PORT_USB_CHARGER_1 MEC1322_I2C0_1
#define I2C_PORT_USB_MUX MEC1322_I2C0_1
#define I2C_PORT_PD_MCU MEC1322_I2C1
#define I2C_PORT_TCPC MEC1322_I2C1
#define I2C_PORT_ALS MEC1322_I2C2
#define I2C_PORT_ACCEL MEC1322_I2C2
#define I2C_PORT_GYRO MEC1322_I2C2
#define I2C_PORT_PMIC MEC1322_I2C0_0
#define I2C_PORT_USB_CHARGER_2 MEC1322_I2C0_0
#define CONFIG_ALS
#define CONFIG_ALS_OPT3001
#define OPT3001_I2C_ADDR OPT3001_I2C_ADDR1
/* Accelerometer */
#ifdef HAS_TASK_MOTIONSENSE
#define CONFIG_ACCEL_KXCJ9
/* TODO: Enable support for gyrometer once space is availble. */
/* #define CONFIG_GYRO_L3GD20H */
#define CONFIG_LID_ANGLE
#define CONFIG_LID_ANGLE_SENSOR_BASE 0
#define CONFIG_LID_ANGLE_SENSOR_LID 1
#endif
/* Modules we want to exclude */
#undef CONFIG_CMD_ACCEL_INFO
#undef CONFIG_CMD_ACCELS
#undef CONFIG_CMD_APTHROTTLE
#undef CONFIG_CMD_BATTFAKE
#undef CONFIG_CMD_HASH
#undef CONFIG_CMD_TEMP_SENSOR
#undef CONFIG_CMD_TIMERINFO
#undef CONFIG_CONSOLE_CMDHELP
#undef CONFIG_CONSOLE_HISTORY
#undef CONFIG_PECI
#ifndef __ASSEMBLER__
#include "gpio_signal.h"
#include "registers.h"
/* ADC signal */
enum adc_channel {
ADC_BATT_PRESENT,
ADC_VBUS,
ADC_AMON_BMON,
ADC_PSYS,
/* Number of ADC channels */
ADC_CH_COUNT
};
/* power signal definitions */
enum power_signal {
X86_RSMRST_L_PWRGD = 0,
X86_SLP_S0_DEASSERTED,
X86_SLP_S3_DEASSERTED,
X86_SLP_S4_DEASSERTED,
X86_SLP_SUS_DEASSERTED,
/* Number of X86 signals */
POWER_SIGNAL_COUNT
};
enum temp_sensor_id {
/* TMP432 local and remote sensors */
TEMP_SENSOR_I2C_TMP432_LOCAL,
TEMP_SENSOR_I2C_TMP432_REMOTE1,
TEMP_SENSOR_I2C_TMP432_REMOTE2,
/* Battery temperature sensor */
TEMP_SENSOR_BATTERY,
TEMP_SENSOR_COUNT
};
/* Light sensors */
enum als_id {
ALS_OPT3001 = 0,
ALS_COUNT,
};
/* start as a sink in case we have no other power supply/battery */
#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
/* TODO: determine the following board specific type-C power constants */
/*
* delay to turn on the power supply max is ~16ms.
* delay to turn off the power supply max is about ~180ms.
*/
#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
/* delay to turn on/off vconn */
#define PD_VCONN_SWAP_DELAY 5000 /* us */
/* Define typical operating power and max power */
#define PD_OPERATING_POWER_MW 15000
#define PD_MAX_POWER_MW 60000
#define PD_MAX_CURRENT_MA 3000
#define PD_MAX_VOLTAGE_MV 20000
/* Reset PD MCU */
void board_reset_pd_mcu(void);
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

15
board/kunimitsu/build.mk
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# -*- makefile -*-
# Copyright 2015 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is SMSC MEC1322 / external SPI is 512KB / external clock is crystal
CHIP:=mec1322
CHIP_SPI_SIZE_KB:=512
board-y=board.o led.o
board-$(CONFIG_BATTERY_SMART)+=battery.o
board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o

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board/kunimitsu/ec.tasklist
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/*
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(ALS, als_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(USB_CHG_P1, usb_charger_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(MOTIONSENSE, motion_sense_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C0, pd_task, NULL, PD_TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C1, pd_task, NULL, PD_TASK_STACK_SIZE)

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board/kunimitsu/gpio.inc
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/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(LID_OPEN, PIN(27), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
GPIO_INT(AC_PRESENT, PIN(30), GPIO_INT_BOTH, extpower_interrupt)
GPIO_INT(WP_L, PIN(33), GPIO_INT_BOTH, switch_interrupt)
/* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */
GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt)
/* RSMRST from PMIC */
GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
GPIO_INT(PCH_SLP_S0_L, PIN(141), GPIO_INT_BOTH, power_signal_interrupt_S0)
GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
GPIO_INT(VOLUME_UP_L, PIN(31), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
GPIO_INT(VOLUME_DOWN_L, PIN(47), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
GPIO_INT(PMIC_INT_L, PIN(50), GPIO_INT_FALLING, power_signal_interrupt)
GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_FALLING, pd_mcu_interrupt)
GPIO_INT(USB_C0_VBUS_WAKE_L,PIN(152), GPIO_INT_BOTH, vbus0_evt)
GPIO_INT(USB_C1_VBUS_WAKE_L,PIN(123), GPIO_INT_BOTH, vbus1_evt)
GPIO_INT(USB_C0_BC12_INT_L, PIN(124), GPIO_INT_FALLING, usb0_evt)
GPIO_INT(USB_C1_BC12_INT_L, PIN(145), GPIO_INT_FALLING, usb1_evt)
#ifdef CONFIG_LOW_POWER_IDLE
GPIO_INT(UART0_RX, PIN(162), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt) /* UART0 RX input */
#endif
/* Puesdo G3 */
GPIO(G3_SLEEP_EN, PIN(55), GPIO_OUT_LOW)
GPIO(PD_RST_L, PIN(130), GPIO_ODR_HIGH)
GPIO(USB2_OTG_ID, PIN(13), GPIO_ODR_LOW)
/* I2C pins - these will be reconfigured for alternate function below */
GPIO(I2C0_0_SCL, PIN(15), GPIO_INPUT)
GPIO(I2C0_0_SDA, PIN(16), GPIO_INPUT)
GPIO(I2C0_1_SCL, PIN(134), GPIO_INPUT)
GPIO(I2C0_1_SDA, PIN(17), GPIO_INPUT)
GPIO(I2C1_SCL, PIN(22), GPIO_INPUT)
GPIO(I2C1_SDA, PIN(23), GPIO_INPUT)
GPIO(I2C2_SCL, PIN(20), GPIO_INPUT)
GPIO(I2C2_SDA, PIN(21), GPIO_INPUT)
GPIO(I2C3_SCL, PIN(24), GPIO_INPUT)
GPIO(I2C3_SDA, PIN(25), GPIO_INPUT)
GPIO(PCH_SCI_L, PIN(26), GPIO_ODR_HIGH)
GPIO(USB1_ENABLE, PIN(36), GPIO_OUT_HIGH)
GPIO(USB2_ENABLE, PIN(67), GPIO_OUT_HIGH)
GPIO(ENTERING_RW, PIN(41), GPIO_OUT_LOW)
GPIO(PCH_SMI_L, PIN(44), GPIO_ODR_HIGH)
GPIO(PCH_PWRBTN_L, PIN(45), GPIO_OUT_HIGH)
GPIO(USB_C0_DP_HPD, PIN(46), GPIO_OUT_LOW)
GPIO(USB_C1_DP_HPD, PIN(51), GPIO_OUT_LOW)
GPIO(CPU_PROCHOT, PIN(52), GPIO_OUT_LOW)
GPIO(ENABLE_TOUCHPAD, PIN(53), GPIO_OUT_LOW)
GPIO(USB_PD_WAKE, PIN(60), GPIO_OUT_LOW)
/* When asserted, ME does not lock security descriptor */
GPIO(PCH_SEC_DISABLE_L, PIN(65), GPIO_ODR_HIGH)
GPIO(PCH_WAKE_L, PIN(66), GPIO_ODR_HIGH)
GPIO(USB2_OTG_VBUSSENSE, PIN(105), GPIO_OUT_LOW)
GPIO(PCH_ACOK, PIN(110), GPIO_OUT_LOW)
/* Interrupts from accelerometer / gyro -- not yet implemented */
GPIO(LID_ACCEL_INT, PIN(161), GPIO_INPUT | GPIO_PULL_DOWN) /* Lid ACCEL sensor interrupt to EC */
GPIO(GYRO_INT, PIN(127), GPIO_INPUT | GPIO_PULL_DOWN) /* Lid Gyro sensor interrupt to EC */
GPIO(BASE_ACCEL_INT, PIN(147), GPIO_INPUT | GPIO_PULL_DOWN) /* Base ACCEL sensor interrupt to EC */
GPIO(GYRO_DRDY, PIN(133), GPIO_INPUT | GPIO_PULL_DOWN) /* Lid Gyro sensor DRDY interrupt to EC */
GPIO(WLAN_OFF_L, PIN(132), GPIO_OUT_HIGH)
/* RCIN# line to PCH for 8042 emulation */
GPIO(PCH_RCIN_L, PIN(135), GPIO_ODR_HIGH)
/* Fan PWM output - NC / testing only */
GPIO(NC_136, PIN(136), GPIO_INPUT | GPIO_PULL_UP) /* Reserved for KBD Backlight */
/* Bring down all rails but RTC rail */
GPIO(LDO_EN, PIN(211), GPIO_OUT_LOW)
GPIO(PCH_RSMRST_L, PIN(143), GPIO_OUT_LOW)
/* prochot input from devices */
GPIO(PLATFORM_EC_PROCHOT, PIN(151), GPIO_INPUT)
GPIO(USB_C0_5V_EN, PIN(154), GPIO_OUT_LOW)
GPIO(USB_C1_5V_EN, PIN(204), GPIO_OUT_LOW)
GPIO(USB_C0_CHARGE_EN_L, PIN(64), GPIO_OUT_LOW)
GPIO(USB_C1_CHARGE_EN_L, PIN(210), GPIO_OUT_LOW)
/* Reserved for USB-A ILIM */
GPIO(USB_ILIM_SEL, PIN(11), GPIO_INPUT | GPIO_PULL_UP)
GPIO(FAN_PWR_DIS_L, PIN(160), GPIO_OUT_HIGH)
GPIO(PCH_RTCRST_L, PIN(163), GPIO_ODR_HIGH)
GPIO(PMIC_SLP_SUS_L, PIN(201), GPIO_OUT_LOW)
GPIO(ENABLE_BACKLIGHT, PIN(202), GPIO_OUT_HIGH)
GPIO(PP3300_WLAN_EN, PIN(203), GPIO_OUT_HIGH)
GPIO(CHG_1A5_EN, PIN(157), GPIO_OUT_HIGH)
GPIO(BOARD_VERSION1, PIN(6), GPIO_INPUT)
GPIO(BOARD_VERSION2, PIN(7), GPIO_INPUT)
GPIO(BOARD_VERSION3, PIN(10), GPIO_INPUT)
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
GPIO(SYS_RESET_L, PIN(121), GPIO_ODR_HIGH)
GPIO(NC_150, PIN(150), GPIO_INPUT | GPIO_PULL_UP)
GPIO(CHARGE_LED1, PIN(155), GPIO_OUT_LOW)
GPIO(CHARGE_LED2, PIN(156), GPIO_OUT_LOW)
/* Alternate functions GPIO definitions */
/* GPIO162(UART_RX), GPIO165(UART_TX) */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* KB pins */
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
/* KB ROW - GPIO000-GPIO005 */
ALTERNATE(PIN_MASK(0, 0x3f), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB ROW - GPIO100-GPIO104, GPIO106-GPIO107 */
ALTERNATE(PIN_MASK(10, 0xdf), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB COL - GPIO032 */
ALTERNATE(PIN_MASK(3, 0x04), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO040, GPIO42-GPIO43 */
ALTERNATE(PIN_MASK(4, 0x0d), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO125-GPIO126 */
ALTERNATE(PIN_MASK(12, 0x60), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO142, GPIO144 */
ALTERNATE(PIN_MASK(14, 0x14), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* LPC pins */
/* LPC_CLK_RUN_L - GPIO014 */
ALTERNATE(PIN_MASK(1, 0x10), 1, MODULE_LPC, 0)
/* LAD[0:3] - GPIO111-GPIO114, SERIRQ - GPIO115, PCI_CLK - GPIO117 */
ALTERNATE(PIN_MASK(11, 0xbe), 1, MODULE_LPC, 0)
/* LRESET# - GPIO116 */
ALTERNATE(PIN_MASK(11, 0x40), 1, MODULE_LPC, GPIO_INT_BOTH)
/* LFRAME# - GPIO120 */
ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0)
/* SPI pins */
/* MOSI - GPIO054 */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
/* MISO - GPIO164 */
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0)
/* PVT_SCLK - GPIO153 */
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)
/* I2C pins */
/* I2C0_0 CLK - GPIO015, I2C0_0 DAT - GPIO016, I2C0_1 DAT - GPIO017 */
ALTERNATE(PIN_MASK(1, 0xe0), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C{1,2,3} CLK / DAT - GPIO020-GPIO025*/
ALTERNATE(PIN_MASK(2, 0x3f), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C0_1 CLK - GPIO134 */
ALTERNATE(PIN_MASK(13, 0x10), 2, MODULE_I2C, GPIO_ODR_HIGH)
/*
* ADC pins
* ADC0 - GPIO056 / EC_BATT_TMP/BATT_BAT_PRESENT_L
* ADC1 - GPIO057 / PPVAR_BOOSTIN_SENSE
*/
ALTERNATE(PIN_MASK(5, 0xC0), 1, MODULE_ADC, GPIO_ANALOG)
/* ADC3 - GPIO061 / IADP_ACMON_BMON. ADC4 - GPIO062 / PMON_PSYS */
ALTERNATE(PIN_MASK(6, 0x06), 1, MODULE_ADC, GPIO_ANALOG)
/* VCC1_RST# - GPIO131 */
ALTERNATE(PIN_MASK(13, 0x02), 1, MODULE_PMU, 0)
/* nRESET_OUT - GPIO121 */
ALTERNATE(PIN_MASK(12, 0x02), 1, MODULE_PMU, 0)
/* RPM-PWM for FAN */
/* TACH2PWM_OUT - GPIO34 */
ALTERNATE(PIN_MASK(3, 0x10), 3, MODULE_PWM, 0)
/* TACH2PWM_IN - GPIO140 */
ALTERNATE(PIN_MASK(14, 0x01), 3, MODULE_PWM, 0)

159
board/kunimitsu/led.c
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Power and battery LED control for Glados.
*/
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "led_common.h"
#include "util.h"
#define BAT_LED_ON 1
#define BAT_LED_OFF 0
#define CRITICAL_LOW_BATTERY_PERCENTAGE 3
#define LOW_BATTERY_PERCENTAGE 10
#define LED_TOTAL_4SECS_TICKS 4
#define LED_TOTAL_2SECS_TICKS 2
#define LED_ON_1SEC_TICKS 1
#define LED_ON_2SECS_TICKS 2
const enum ec_led_id supported_led_ids[] = {
EC_LED_ID_BATTERY_LED};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
enum led_color {
LED_OFF = 0,
LED_BLUE,
LED_AMBER,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
static int bat_led_set_color(enum led_color color)
{
switch (color) {
case LED_OFF:
gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
break;
case LED_BLUE:
gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_ON);
gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_OFF);
break;
case LED_AMBER:
gpio_set_level(GPIO_BAT_LED_BLUE, BAT_LED_OFF);
gpio_set_level(GPIO_BAT_LED_AMBER, BAT_LED_ON);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
brightness_range[EC_LED_COLOR_BLUE] = 1;
brightness_range[EC_LED_COLOR_AMBER] = 1;
}
static int kunimitsu_led_set_color_battery(enum led_color color)
{
return bat_led_set_color(color);
}
static int kunimitsu_led_set_color(enum ec_led_id led_id, enum led_color color)
{
int rv;
led_auto_control(led_id, 0);
switch (led_id) {
case EC_LED_ID_BATTERY_LED:
rv = kunimitsu_led_set_color_battery(color);
break;
default:
return EC_ERROR_UNKNOWN;
}
return rv;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
if (brightness[EC_LED_COLOR_BLUE] != 0)
kunimitsu_led_set_color(led_id, LED_BLUE);
else if (brightness[EC_LED_COLOR_AMBER] != 0)
kunimitsu_led_set_color(led_id, LED_AMBER);
else
kunimitsu_led_set_color(led_id, LED_OFF);
return EC_SUCCESS;
}
static void kunimitsu_led_set_battery(void)
{
static int battery_ticks;
uint32_t chflags = charge_get_flags();
battery_ticks++;
/* BAT LED behavior:
* Same as the chromeos spec
* Green/Amber for CHARGE_FLAG_FORCE_IDLE
*/
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
kunimitsu_led_set_color_battery(LED_AMBER);
break;
case PWR_STATE_DISCHARGE:
/* Less than 3%, blink one second every two second */
if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
charge_get_percent() < CRITICAL_LOW_BATTERY_PERCENTAGE)
kunimitsu_led_set_color_battery(
(battery_ticks % LED_TOTAL_2SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
/* Less than 10%, blink one second every four seconds */
else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
charge_get_percent() < LOW_BATTERY_PERCENTAGE)
kunimitsu_led_set_color_battery(
(battery_ticks % LED_TOTAL_4SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
else
kunimitsu_led_set_color_battery(LED_OFF);
break;
case PWR_STATE_ERROR:
kunimitsu_led_set_color_battery(
(battery_ticks % LED_TOTAL_2SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
break;
case PWR_STATE_CHARGE_NEAR_FULL:
kunimitsu_led_set_color_battery(LED_BLUE);
break;
case PWR_STATE_IDLE: /* External power connected in IDLE */
if (chflags & CHARGE_FLAG_FORCE_IDLE)
kunimitsu_led_set_color_battery(
(battery_ticks % LED_TOTAL_4SECS_TICKS <
LED_ON_2SECS_TICKS) ? LED_AMBER : LED_BLUE);
else
kunimitsu_led_set_color_battery(LED_BLUE);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
/** * Called by hook task every 1 sec */
static void led_second(void)
{
if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
kunimitsu_led_set_battery();
}
DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);

22
board/kunimitsu/lfw/gpio.inc
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@@ -1,22 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Minimal set of GPIOs needed for LFW loader
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
/* SPI PVT chip select */
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
/* Alternate functions GPIO definition */
/* UART */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* SPI pins */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)

399
board/kunimitsu/usb_pd_policy.c
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@@ -1,399 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "atomic.h"
#include "charge_manager.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_mux.h"
#include "usb_pd.h"
#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
PDO_FIXED_COMM_CAP)
/* TODO: fill in correct source and sink capabilities */
const uint32_t pd_src_pdo[] = {
PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
};
const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
const uint32_t pd_snk_pdo[] = {
PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
PDO_BATT(4750, 21000, 15000),
PDO_VAR(4750, 21000, 3000),
};
const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
int pd_is_valid_input_voltage(int mv)
{
return 1;
}
void pd_transition_voltage(int idx)
{
/* No-operation: we are always 5V */
}
int pd_set_power_supply_ready(int port)
{
/* Disable charging */
gpio_set_level(port ? GPIO_USB_C1_CHARGE_EN_L :
GPIO_USB_C0_CHARGE_EN_L, 1);
/* Provide VBUS */
gpio_set_level(port ? GPIO_USB_C1_5V_EN :
GPIO_USB_C0_5V_EN, 1);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
return EC_SUCCESS; /* we are ready */
}
void pd_power_supply_reset(int port)
{
/* Disable VBUS */
gpio_set_level(port ? GPIO_USB_C1_5V_EN :
GPIO_USB_C0_5V_EN, 0);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
void pd_set_input_current_limit(int port, uint32_t max_ma,
uint32_t supply_voltage)
{
#ifdef CONFIG_CHARGE_MANAGER
struct charge_port_info charge;
charge.current = max_ma;
charge.voltage = supply_voltage;
charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge);
#endif
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
void typec_set_input_current_limit(int port, uint32_t max_ma,
uint32_t supply_voltage)
{
#ifdef CONFIG_CHARGE_MANAGER
struct charge_port_info charge;
charge.current = max_ma;
charge.voltage = supply_voltage;
charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge);
#endif
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
int pd_snk_is_vbus_provided(int port)
{
return !gpio_get_level(port ? GPIO_USB_C1_VBUS_WAKE_L :
GPIO_USB_C0_VBUS_WAKE_L);
}
int pd_board_checks(void)
{
return EC_SUCCESS;
}
int pd_check_power_swap(int port)
{
/*
* Allow power swap as long as we are acting as a dual role device,
* otherwise assume our role is fixed (not in S0 or console command
* to fix our role).
*/
return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0;
}
int pd_check_data_swap(int port, int data_role)
{
/* Allow data swap if we are a UFP, otherwise don't allow */
return (data_role == PD_ROLE_UFP) ? 1 : 0;
}
int pd_check_vconn_swap(int port)
{
/* in G3, do not allow vconn swap since pp5000_A rail is off */
return gpio_get_level(GPIO_PMIC_SLP_SUS_L);
}
void pd_execute_data_swap(int port, int data_role)
{
/* Do nothing */
}
void pd_check_pr_role(int port, int pr_role, int flags)
{
/*
* If partner is dual-role power and dualrole toggling is on, consider
* if a power swap is necessary.
*/
if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
pd_get_dual_role() == PD_DRP_TOGGLE_ON) {
/*
* If we are a sink and partner is not externally powered, then
* swap to become a source. If we are source and partner is
* externally powered, swap to become a sink.
*/
int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER;
if ((!partner_extpower && pr_role == PD_ROLE_SINK) ||
(partner_extpower && pr_role == PD_ROLE_SOURCE))
pd_request_power_swap(port);
}
}
void pd_check_dr_role(int port, int dr_role, int flags)
{
/* If UFP, try to switch to DFP */
if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
pd_request_data_swap(port);
}
/* ----------------- Vendor Defined Messages ------------------ */
const struct svdm_response svdm_rsp = {
.identity = NULL,
.svids = NULL,
.modes = NULL,
};
int pd_custom_vdm(int port, int cnt, uint32_t *payload,
uint32_t **rpayload)
{
int cmd = PD_VDO_CMD(payload[0]);
uint16_t dev_id = 0;
int is_rw;
/* make sure we have some payload */
if (cnt == 0)
return 0;
switch (cmd) {
case VDO_CMD_VERSION:
/* guarantee last byte of payload is null character */
*(payload + cnt - 1) = 0;
CPRINTF("version: %s\n", (char *)(payload+1));
break;
case VDO_CMD_READ_INFO:
case VDO_CMD_SEND_INFO:
/* copy hash */
if (cnt == 7) {
dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
is_rw = VDO_INFO_IS_RW(payload[6]);
CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
HW_DEV_ID_MAJ(dev_id),
HW_DEV_ID_MIN(dev_id),
VDO_INFO_SW_DBG_VER(payload[6]),
is_rw);
} else if (cnt == 6) {
/* really old devices don't have last byte */
pd_dev_store_rw_hash(port, dev_id, payload + 1,
SYSTEM_IMAGE_UNKNOWN);
}
break;
case VDO_CMD_CURRENT:
CPRINTF("Current: %dmA\n", payload[1]);
break;
case VDO_CMD_FLIP:
usb_mux_flip(port);
break;
#ifdef CONFIG_USB_PD_LOGGING
case VDO_CMD_GET_LOG:
pd_log_recv_vdm(port, cnt, payload);
break;
#endif /* CONFIG_USB_PD_LOGGING */
}
return 0;
}
#ifdef CONFIG_USB_PD_ALT_MODE_DFP
static int dp_flags[CONFIG_USB_PD_PORT_COUNT];
/* DP Status VDM as returned by UFP */
static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT];
static void svdm_safe_dp_mode(int port)
{
/* make DP interface safe until configure */
dp_flags[port] = 0;
dp_status[port] = 0;
usb_mux_set(port, TYPEC_MUX_NONE,
USB_SWITCH_CONNECT, pd_get_polarity(port));
}
static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
{
/* Only enter mode if device is DFP_D capable */
if (mode_caps & MODE_DP_SNK) {
svdm_safe_dp_mode(port);
return 0;
}
return -1;
}
static int svdm_dp_status(int port, uint32_t *payload)
{
int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
CMD_DP_STATUS | VDO_OPOS(opos));
payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */
0, /* HPD level ... not applicable */
0, /* exit DP? ... no */
0, /* usb mode? ... no */
0, /* multi-function ... no */
(!!(dp_flags[port] & DP_FLAGS_DP_ON)),
0, /* power low? ... no */
(!!(dp_flags[port] & DP_FLAGS_DP_ON)));
return 2;
};
static int svdm_dp_config(int port, uint32_t *payload)
{
int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
if (!pin_mode)
return 0;
usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP,
USB_SWITCH_CONNECT, pd_get_polarity(port));
payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
CMD_DP_CONFIG | VDO_OPOS(opos));
payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
1, /* DPv1.3 signaling */
2); /* UFP connected */
return 2;
};
#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD)
static void svdm_dp_post_config(int port)
{
dp_flags[port] |= DP_FLAGS_DP_ON;
if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
return;
gpio_set_level(PORT_TO_HPD(port), 1);
}
static void hpd0_irq_deferred(void)
{
gpio_set_level(GPIO_USB_C0_DP_HPD, 1);
}
static void hpd1_irq_deferred(void)
{
gpio_set_level(GPIO_USB_C1_DP_HPD, 1);
}
DECLARE_DEFERRED(hpd0_irq_deferred);
DECLARE_DEFERRED(hpd1_irq_deferred);
#define PORT_TO_HPD_IRQ_DEFERRED(port) ((port) ? \
&hpd1_irq_deferred_data : \
&hpd0_irq_deferred_data)
static int svdm_dp_attention(int port, uint32_t *payload)
{
int cur_lvl;
int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
enum gpio_signal hpd = PORT_TO_HPD(port);
cur_lvl = gpio_get_level(hpd);
dp_status[port] = payload[1];
/* Its initial DP status message prior to config */
if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
if (lvl)
dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
return 1;
}
if (irq & cur_lvl) {
gpio_set_level(hpd, 0);
hook_call_deferred(PORT_TO_HPD_IRQ_DEFERRED(port),
HPD_DSTREAM_DEBOUNCE_IRQ);
} else if (irq & !cur_lvl) {
CPRINTF("ERR:HPD:IRQ&LOW\n");
return 0; /* nak */
} else {
gpio_set_level(hpd, lvl);
}
/* ack */
return 1;
}
static void svdm_exit_dp_mode(int port)
{
svdm_safe_dp_mode(port);
gpio_set_level(PORT_TO_HPD(port), 0);
}
static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
{
/* Always enter GFU mode */
return 0;
}
static void svdm_exit_gfu_mode(int port)
{
}
static int svdm_gfu_status(int port, uint32_t *payload)
{
/*
* This is called after enter mode is successful, send unstructured
* VDM to read info.
*/
pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
return 0;
}
static int svdm_gfu_config(int port, uint32_t *payload)
{
return 0;
}
static int svdm_gfu_attention(int port, uint32_t *payload)
{
return 0;
}
const struct svdm_amode_fx supported_modes[] = {
{
.svid = USB_SID_DISPLAYPORT,
.enter = &svdm_enter_dp_mode,
.status = &svdm_dp_status,
.config = &svdm_dp_config,
.post_config = &svdm_dp_post_config,
.attention = &svdm_dp_attention,
.exit = &svdm_exit_dp_mode,
},
{
.svid = USB_VID_GOOGLE,
.enter = &svdm_enter_gfu_mode,
.status = &svdm_gfu_status,
.config = &svdm_gfu_config,
.attention = &svdm_gfu_attention,
.exit = &svdm_exit_gfu_mode,
}
};
const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
#endif /* CONFIG_USB_PD_ALT_MODE_DFP */

1
board/kunimitsu_pd
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@@ -1 +0,0 @@
glados_pd/

1
board/lars/Makefile
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@@ -1 +0,0 @@
../../Makefile

45
board/lars/battery.c
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@@ -1,45 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define SB_SHIP_MODE_REG 0x3a
#define SB_SHUTDOWN_DATA 0xC574
static const struct battery_info info = {
.voltage_max = 13050,/* mV */
.voltage_normal = 11400,
.voltage_min = 9100,
.precharge_current = 256,/* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 50,
.charging_min_c = 0,
.charging_max_c = 60,
.discharging_min_c = -20,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
int rv;
/* Ship mode command must be sent twice to take effect */
rv = sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
if (rv != EC_SUCCESS)
return rv;
return sb_write(SB_SHIP_MODE_REG, SB_SHUTDOWN_DATA);
}

562
board/lars/board.c
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@@ -1,562 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Skylake Chrome Reference Design board-specific configuration */
#include "adc_chip.h"
#include "charge_manager.h"
#include "charge_state.h"
#include "charger.h"
#include "console.h"
#include "driver/pmic_tps650830.h"
#include "driver/tcpm/tcpci.h"
#include "driver/temp_sensor/tmp432.h"
#include "extpower.h"
#include "fan.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "i2c.h"
#include "lid_switch.h"
#include "math_util.h"
#include "motion_lid.h"
#include "motion_sense.h"
#include "pi3usb9281.h"
#include "power.h"
#include "power_button.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "spi.h"
#include "switch.h"
#include "system.h"
#include "task.h"
#include "temp_sensor.h"
#include "temp_sensor_chip.h"
#include "thermal.h"
#include "timer.h"
#include "uart.h"
#include "usb_charge.h"
#include "usb_mux.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "util.h"
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
#define TPS650830_I2C_ADDR TPS650830_I2C_ADDR1
/* Exchange status with PD MCU. */
static void pd_mcu_interrupt(enum gpio_signal signal)
{
#ifdef HAS_TASK_PDCMD
/* Exchange status with PD MCU to determine interrupt cause */
host_command_pd_send_status(0);
#endif
}
void vbus0_evt(enum gpio_signal signal)
{
/* VBUS present GPIO is inverted */
usb_charger_vbus_change(0, !gpio_get_level(signal));
task_wake(TASK_ID_PD_C0);
}
void usb0_evt(enum gpio_signal signal)
{
task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12, 0);
}
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_RSMRST_L_PGOOD, 1, "RSMRST_N_PWRGD"},
{GPIO_PCH_SLP_S0_L, 1, "SLP_S0_DEASSERTED"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"},
{GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"},
{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS_DEASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* VBUS_MUL */
#define VBUS_MUL 30405
/* VBUS_DIV 10bit ADC */
#define VBUS_DIV 1024
/* VBUS_SHIFT */
#define VBUS_SHIFT 16
/* ADC channels */
const struct adc_t adc_channels[] = {
/* Vbus sensing. Converted to mV, full ADC is equivalent to 30V. */
[ADC_VBUS] = {"VBUS", VBUS_MUL, VBUS_DIV, VBUS_SHIFT, 1},
/* Adapter current output or battery discharging current */
[ADC_AMON_BMON] = {"AMON_BMON", 25000, 3072, 0, 3},
/*
* System current consumption. Converted to mV,
* full ADC is equivalent to 100W
*/
[ADC_PSYS] = {"PSYS", 3000, 1024, 0, 4},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{1, 0},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
const struct i2c_port_t i2c_ports[] = {
{"pmic", MEC1322_I2C0_0, 400, GPIO_I2C0_0_SCL, GPIO_I2C0_0_SDA},
{"muxes", MEC1322_I2C0_1, 400, GPIO_I2C0_1_SCL, GPIO_I2C0_1_SDA},
{"pd_mcu", MEC1322_I2C1, 500, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
{"batt", MEC1322_I2C3, 100, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = {
{I2C_PORT_TCPC, CONFIG_TCPC_I2C_BASE_ADDR, &tcpci_tcpm_drv},
};
/* Physical fans. These are logically separate from pwm_channels. */
const struct fan_t fans[] = {
{.flags = FAN_USE_RPM_MODE,
.rpm_min = 1000,
.rpm_start = 1000,
.rpm_max = 5200,
.ch = 1,
.pgood_gpio = -1,
.enable_gpio = GPIO_FAN_PWR_DIS_L,
},
};
BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
/* SPI devices */
const struct spi_device_t spi_devices[] = {
{ CONFIG_SPI_FLASH_PORT, 0, GPIO_PVT_CS0},
};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
const enum gpio_signal hibernate_wake_pins[] = {
GPIO_AC_PRESENT,
GPIO_LID_OPEN,
GPIO_POWER_BUTTON_L,
};
const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
struct pi3usb9281_config pi3usb9281_chips[] = {
{
.i2c_port = I2C_PORT_USB_CHARGER_1,
.mux_lock = NULL,
},
};
BUILD_ASSERT(ARRAY_SIZE(pi3usb9281_chips) ==
CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT);
struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = {
{
.port_addr = 0xa8,
.driver = &pi3usb30532_usb_mux_driver,
}
};
/**
* Reset PD MCU
*/
void board_reset_pd_mcu(void)
{
gpio_set_level(GPIO_PD_RST_L, 0);
usleep(100);
gpio_set_level(GPIO_PD_RST_L, 1);
}
#ifdef HAS_TASK_MOTIONSENSE
/* Four Motion sensors */
/* kxcj9 mutex and local/private data*/
static struct mutex g_kxcj9_mutex[2];
struct kionix_accel_data g_kxcj9_data[2] = {
{.variant = KXCJ9},
{.variant = KXCJ9},
};
/* Matrix to rotate accelrator into standard reference frame */
const matrix_3x3_t base_standard_ref = {
{ 0, FLOAT_TO_FP(1), 0},
{FLOAT_TO_FP(-1), 0, 0},
{ 0, 0, FLOAT_TO_FP(1)}
};
const matrix_3x3_t lid_standard_ref = {
{FLOAT_TO_FP(-1), 0, 0},
{ 0, FLOAT_TO_FP(-1), 0},
{ 0, 0, FLOAT_TO_FP(-1)}
};
struct motion_sensor_t motion_sensors[] = {
{.name = "Base Accel",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_KXCJ9,
.type = MOTIONSENSE_TYPE_ACCEL,
.location = MOTIONSENSE_LOC_BASE,
.drv = &kionix_accel_drv,
.mutex = &g_kxcj9_mutex[0],
.drv_data = &g_kxcj9_data[0],
.port = I2C_PORT_ACCEL,
.addr = KXCJ9_ADDR1,
.rot_standard_ref = &base_standard_ref,
.default_range = 2, /* g, enough for laptop. */
.config = {
/* AP: by default shutdown all sensors */
[SENSOR_CONFIG_AP] = {
.odr = 0,
.ec_rate = 0,
},
/* EC use accel for angle detection */
[SENSOR_CONFIG_EC_S0] = {
.odr = 100000 | ROUND_UP_FLAG,
.ec_rate = 100 * MSEC,
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S3] = {
.odr = 0,
.ec_rate = 0
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S5] = {
.odr = 0,
.ec_rate = 0
},
},
},
{.name = "Lid Accel",
.active_mask = SENSOR_ACTIVE_S0,
.chip = MOTIONSENSE_CHIP_KXCJ9,
.type = MOTIONSENSE_TYPE_ACCEL,
.location = MOTIONSENSE_LOC_LID,
.drv = &kionix_accel_drv,
.mutex = &g_kxcj9_mutex[1],
.drv_data = &g_kxcj9_data[1],
.port = I2C_PORT_ACCEL,
.addr = KXCJ9_ADDR0,
.rot_standard_ref = &lid_standard_ref,
.default_range = 2, /* g, enough for laptop. */
.config = {
/* AP: by default shutdown all sensors */
[SENSOR_CONFIG_AP] = {
.odr = 0,
.ec_rate = 0,
},
/* EC use accel for angle detection */
[SENSOR_CONFIG_EC_S0] = {
.odr = 100000 | ROUND_UP_FLAG,
.ec_rate = 100 * MSEC,
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S3] = {
.odr = 0,
.ec_rate = 0
},
/* Sensor off in S3/S5 */
[SENSOR_CONFIG_EC_S5] = {
.odr = 0,
.ec_rate = 0
},
},
},
};
const unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors);
#endif
/*
* Temperature sensors data; must be in same order as enum temp_sensor_id.
* Sensor index and name must match those present in coreboot:
* src/mainboard/google/${board}/acpi/dptf.asl
*/
const struct temp_sensor_t temp_sensors[] = {
{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_LOCAL, 4},
{"TMP432_Sensor_1", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_REMOTE1, 4},
{"TMP432_Sensor_2", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_REMOTE2, 4},
{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_temp_sensor_get_val,
0, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/*
* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
* same order as enum temp_sensor_id. To always ignore any temp, use 0.
*/
struct ec_thermal_config thermal_params[] = {
/* {Twarn, Thigh, Thalt}, fan_off, fan_max */
{{0, 0, 0}, 0, 0}, /* TMP432_Internal */
{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_1 */
{{0, 0, 0}, 0, 0}, /* TMP432_Sensor_2 */
{{0, 0, 0}, 0, 0}, /* Battery */
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
/* Initialize PMIC */
#define I2C_PMIC_READ(reg, data) \
i2c_read8(I2C_PORT_PMIC, TPS650830_I2C_ADDR, (reg), (data))
#define I2C_PMIC_WRITE(reg, data) \
i2c_write8(I2C_PORT_PMIC, TPS650830_I2C_ADDR, (reg), (data))
static void board_pmic_init(void)
{
int ret;
int data;
int error_count = 0;
/* No need to re-init PMIC since settings are sticky across sysjump */
if (system_jumped_to_this_image())
return;
/* Read vendor ID */
while (1) {
ret = I2C_PMIC_READ(TPS650830_REG_VENDORID, &data);
if (!ret && data == TPS650830_VENDOR_ID) {
break;
} else if (error_count > 5)
goto pmic_error;
error_count++;
}
/*
* VCCIOCNT register setting
* [6] : CSDECAYEN
* otherbits: default
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_VCCIOCNT, 0x4A);
if (ret)
goto pmic_error;
/*
* VRMODECTRL:
* [4] : VCCIOLPM clear
* otherbits: default
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_VRMODECTRL, 0x2F);
if (ret)
goto pmic_error;
/*
* PGMASK1 : Exclude VCCIO from Power Good Tree
* [7] : MVCCIOPG clear
* otherbits: default
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_PGMASK1, 0x80);
if (ret)
goto pmic_error;
/*
* PWFAULT_MASK1 Register settings
* [7] : 1b V4 Power Fault Masked
* [4] : 1b V7 Power Fault Masked
* [2] : 1b V9 Power Fault Masked
* [0] : 1b V13 Power Fault Masked
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_PWFAULT_MASK1, 0x95);
if (ret)
goto pmic_error;
/*
* Discharge control 4 register configuration
* [7:6] : 00b Reserved
* [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm
* [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm
* [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT4, 0x15);
if (ret)
goto pmic_error;
/*
* Discharge control 3 register configuration
* [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm
* [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm
* [3:2] : 01b V100A discharge resistance (V11), 100 Ohm
* [1:0] : 01b V085A discharge resistance (V12), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT3, 0x55);
if (ret)
goto pmic_error;
/*
* Discharge control 2 register configuration
* [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm
* [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm
* [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm
* [1:0] : 01b V18A discharge resistance (V8), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT2, 0x55);
if (ret)
goto pmic_error;
/*
* Discharge control 1 register configuration
* [7:2] : 00b Reserved
* [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT1, 0x01);
if (ret)
goto pmic_error;
/*
* Increase Voltage
* [7:0] : 0x2a default
* [5:4] : 10b default
* [5:4] : 01b 5.1V (0x1a)
*/
ret = I2C_PMIC_WRITE(TPS650830_REG_V5ADS3CNT, 0x1a);
if (ret)
goto pmic_error;
CPRINTS("PMIC initialization done");
return;
pmic_error:
CPRINTS("PMIC initialization failed");
}
DECLARE_HOOK(HOOK_INIT, board_pmic_init, HOOK_PRIO_INIT_I2C + 1);
/* Initialize board. */
static void board_init(void)
{
/* Enable PD MCU interrupt */
gpio_enable_interrupt(GPIO_PD_MCU_INT);
/* Enable VBUS interrupt */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
/* Enable pericom BC1.2 interrupts */
gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_L);
/* Provide AC status to the PCH */
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/**
* Buffer the AC present GPIO to the PCH.
*/
static void board_extpower(void)
{
gpio_set_level(GPIO_PCH_ACOK, extpower_is_present());
}
DECLARE_HOOK(HOOK_AC_CHANGE, board_extpower, HOOK_PRIO_DEFAULT);
/**
* Set active charge port -- only one port can be active at a time.
*
* @param charge_port Charge port to enable.
*
* Returns EC_SUCCESS if charge port is accepted and made active,
* EC_ERROR_* otherwise.
*/
int board_set_active_charge_port(int charge_port)
{
/* check if we are source vbus on that port */
int source = gpio_get_level(GPIO_USB_C0_5V_EN);
/* charge port is a realy physical port */
if ((charge_port == 0) && source) {
CPRINTS("Skip enable p%d", charge_port);
return EC_ERROR_INVAL;
}
CPRINTS("New chg p%d", charge_port);
if (charge_port == CHARGE_PORT_NONE) {
/* Disable charge ports */
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
} else {
/* We have only one port, no need to
make sure non-charging port is disabled */
/* Enable charging port */
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 0);
}
return EC_SUCCESS;
}
/**
* Set the charge limit based upon desired maximum.
*
* @param charge_ma Desired charge limit (mA).
*/
void board_set_charge_limit(int charge_ma)
{
charge_set_input_current_limit(MAX(charge_ma,
CONFIG_CHARGER_INPUT_CURRENT));
}
/* Enable touchpad on chipset startup so that it can wake the system */
static void board_chipset_startup(void)
{
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
}
DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup,
HOOK_PRIO_DEFAULT);
/* Disable touchpad on chipset shutdown as it is no longer useful */
static void board_chipset_shutdown(void)
{
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
}
DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown,
HOOK_PRIO_DEFAULT);
/* Make the pmic re-sequence the power rails under these conditions. */
#define PMIC_RESET_FLAGS \
(RESET_FLAG_WATCHDOG | RESET_FLAG_SOFT | RESET_FLAG_HARD)
static void board_handle_reboot(void)
{
int flags;
if (system_jumped_to_this_image())
return;
/* Interrogate current reset flags from previous reboot. */
flags = system_get_reset_flags();
if (!(flags & PMIC_RESET_FLAGS))
return;
/* Preserve AP off request. */
if (flags & RESET_FLAG_AP_OFF)
chip_save_reset_flags(RESET_FLAG_AP_OFF);
ccprintf("Restarting system with PMIC.\n");
/* Flush console */
cflush();
/* Bring down all rails but RTC rail (including EC power). */
gpio_set_level(GPIO_LDO_EN, 1);
while (1)
; /* wait here */
}
DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
void board_hibernate(void)
{
CPRINTS("Enter Pseudo G3");
/*
* Clean up the UART buffer and prevent any unwanted garbage characters
* before power off and also ensure above debug message is printed.
*/
cflush();
gpio_set_level(GPIO_G3_SLEEP_EN, 1);
/* Power to EC should shut down now */
while (1)
;
}

207
board/lars/board.h
View File

@@ -1,207 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Lars: Skylake Chrome Reference Design board configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/*
* Allow dangerous commands.
* TODO: Remove this config before production.
*/
#define CONFIG_SYSTEM_UNLOCKED
/* Optional features */
#define CONFIG_ADC
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_VERSION
#define CONFIG_CMD_ALS
#define CONFIG_CHARGE_MANAGER
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V2
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_ISL9237
#define CONFIG_CHARGER_ILIM_PIN_DISABLED
#define CONFIG_CHARGER_INPUT_CURRENT 512
#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1
#define CONFIG_CHARGER_NARROW_VDC
#define CONFIG_TRICKLE_CHARGING
/* PSYS resistor 8.25KOhm */
#define CHARGER_PSYS_RESISTOR 8250
#define CONFIG_FANS 1
#define CONFIG_CHARGER_PSYS
#define CONFIG_CHARGER_SENSE_RESISTOR 10
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
/*
* PSYS gain = 1 / (PYSY resistor * (1.44 or 0.36) uA/W)
*/
#define ISL9237_C2_PSYS_GAIN_1_44 (100000000ul / (CHARGER_PSYS_RESISTOR * 144))
#define ISL9237_C2_PSYS_GAIN_0_36 (100000000ul / (CHARGER_PSYS_RESISTOR * 36))
#define CONFIG_CHIPSET_SKYLAKE
#define CONFIG_CHIPSET_RESET_HOOK
#define CONFIG_CLOCK_CRYSTAL
#undef CONFIG_DEBUG_ASSERT
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_HOSTCMD_PD
#define CONFIG_I2C
#define CONFIG_I2C_MASTER
#define CONFIG_KEYBOARD_COL2_INVERTED
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_COMMON
#define CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
/* Enable S0IX */
#define CONFIG_POWER_S0IX
#define CONFIG_PWM
#define CONFIG_PWM_KBLIGHT
/* All data won't fit in data RAM. So, moving boundary slightly. */
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE (104 * 1024)
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* We're space constrained on lars, so reduce the UART TX buffer size. */
#undef CONFIG_UART_TX_BUF_SIZE
#define CONFIG_UART_TX_BUF_SIZE 512
#define CONFIG_USB_CHARGER
#define CONFIG_USB_MUX_PI3USB30532
#define CONFIG_USB_POWER_DELIVERY
#define CONFIG_USB_PD_ALT_MODE
#define CONFIG_USB_PD_ALT_MODE_DFP
#define CONFIG_USB_PD_COMM_LOCKED
#define CONFIG_USB_PD_CUSTOM_VDM
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_LOGGING
#define CONFIG_USB_PD_LOG_SIZE 128
#define CONFIG_USB_PD_PORT_COUNT 1
#define CONFIG_USB_PD_TCPM_TCPCI
#define CONFIG_USB_PD_TRY_SRC
#define CONFIG_USB_SWITCH_PI3USB9281
#define CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT 1
#define CONFIG_USBC_SS_MUX
#define CONFIG_USBC_SS_MUX_DFP_ONLY
#define CONFIG_USBC_VCONN
/* USB-A ports */
#define USB_PORT_COUNT 2
#define CONFIG_USB_PORT_POWER_DUMB
#define CONFIG_VBOOT_HASH
#define CONFIG_SPI_FLASH_PORT 1
#define CONFIG_SPI_FLASH
#define CONFIG_FLASH_SIZE 524288
#define CONFIG_SPI_FLASH_W25X40
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_TMP432
/*
* Enable 1 slot of secure temporary storage to support
* suspend/resume with read/write memory training.
*/
#define CONFIG_VSTORE
#define CONFIG_VSTORE_SLOT_COUNT 1
#define CONFIG_WATCHDOG_HELP
/* I2C ports */
#define I2C_PORT_PMIC MEC1322_I2C0_0
#define I2C_PORT_USB_CHARGER_1 MEC1322_I2C0_1
#define I2C_PORT_USB_MUX MEC1322_I2C0_1
#define I2C_PORT_PD_MCU MEC1322_I2C1
#define I2C_PORT_TCPC MEC1322_I2C1
#define I2C_PORT_BATTERY MEC1322_I2C3
#define I2C_PORT_CHARGER MEC1322_I2C3
#define I2C_PORT_THERMAL MEC1322_I2C3
/* Modules we want to exclude */
#undef CONFIG_CMD_ACCEL_INFO
#undef CONFIG_CMD_ACCELS
#undef CONFIG_CMD_HASH
#undef CONFIG_CMD_TEMP_SENSOR
#undef CONFIG_CMD_TIMERINFO
#undef CONFIG_CONSOLE_CMDHELP
#undef CONFIG_CONSOLE_HISTORY
#undef CONFIG_PECI
#ifndef __ASSEMBLER__
#include "gpio_signal.h"
#include "registers.h"
/* ADC signal */
enum adc_channel {
ADC_VBUS,
ADC_AMON_BMON,
ADC_PSYS,
/* Number of ADC channels */
ADC_CH_COUNT
};
enum pwm_channel {
PWM_CH_KBLIGHT,
/* Number of PWM channels */
PWM_CH_COUNT,
};
/* power signal definitions */
enum power_signal {
X86_RSMRST_L_PWRGD = 0,
X86_SLP_S0_DEASSERTED,
X86_SLP_S3_DEASSERTED,
X86_SLP_S4_DEASSERTED,
X86_SLP_SUS_DEASSERTED,
/* Number of X86 signals */
POWER_SIGNAL_COUNT
};
enum temp_sensor_id {
/* TMP432 local and remote sensors */
TEMP_SENSOR_I2C_TMP432_LOCAL,
TEMP_SENSOR_I2C_TMP432_REMOTE1,
TEMP_SENSOR_I2C_TMP432_REMOTE2,
/* Battery temperature sensor */
TEMP_SENSOR_BATTERY,
TEMP_SENSOR_COUNT
};
/* start as a sink in case we have no other power supply/battery */
#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
/* TODO: determine the following board specific type-C power constants */
/*
* delay to turn on the power supply max is ~16ms.
* delay to turn off the power supply max is about ~180ms.
*/
#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
/* Define typical operating power and max power */
#define PD_OPERATING_POWER_MW 15000
#define PD_MAX_POWER_MW 60000
#define PD_MAX_CURRENT_MA 3000
#define PD_MAX_VOLTAGE_MV 20000
/* Reset PD MCU */
void board_reset_pd_mcu(void);
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

15
board/lars/build.mk
View File

@@ -1,15 +0,0 @@
# -*- makefile -*-
# Copyright 2015 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is SMSC MEC1322 / external SPI is 512KB / external clock is crystal
CHIP:=mec1322
CHIP_SPI_SIZE_KB:=512
board-y=board.o led.o
board-$(CONFIG_BATTERY_SMART)+=battery.o
board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o

31
board/lars/ec.tasklist
View File

@@ -1,31 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/*
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(USB_CHG_P0, usb_charger_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE)

173
board/lars/gpio.inc
View File

@@ -1,173 +0,0 @@
/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
/* RSMRST from PMIC */
GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt)
#ifdef CONFIG_LOW_POWER_IDLE
/* UART0 RX input */
GPIO_INT(UART0_RX, PIN(162), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
#endif
GPIO_INT(PMIC_INT_L, PIN(50), GPIO_INT_FALLING, power_signal_interrupt) /* Empty */
GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(152), GPIO_INT_BOTH, vbus0_evt)
GPIO_INT(LID_OPEN, PIN(27), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
GPIO_INT(AC_PRESENT, PIN(30), GPIO_INT_BOTH, extpower_interrupt)
GPIO_INT(WP_L, PIN(33), GPIO_INT_BOTH, switch_interrupt)
/* Buffered power button input from PMIC / ROP_EC_PWR_BTN_L_R */
GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt)
GPIO_INT(PCH_SLP_S0_L, PIN(141), GPIO_INT_BOTH, power_signal_interrupt_S0)
GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
/* RSMRST from PMIC */
GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt)
GPIO_INT(USB_C0_BC12_INT_L, PIN(124), GPIO_INT_FALLING, usb0_evt)
GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_FALLING, pd_mcu_interrupt)
GPIO(BOARD_VERSION1, PIN(6), GPIO_INPUT)
GPIO(BOARD_VERSION2, PIN(7), GPIO_INPUT)
GPIO(BOARD_VERSION3, PIN(10), GPIO_INPUT)
/* Reserved for USB-A ILIM */
GPIO(USB_ILIM_SEL, PIN(11), GPIO_INPUT | GPIO_PULL_UP)
GPIO(PCH_SMI_L, PIN(44), GPIO_ODR_HIGH)
GPIO(PCH_SCI_L, PIN(26), GPIO_ODR_HIGH)
GPIO(SYS_RESET_L, PIN(121), GPIO_ODR_HIGH)
GPIO(PCH_RSMRST_L, PIN(143), GPIO_OUT_LOW)
GPIO(USB_C0_DP_HPD, PIN(46), GPIO_OUT_LOW)
GPIO(NC_047, PIN(47), GPIO_INPUT | GPIO_PULL_UP)
/* When asserted, ME does not lock security descriptor */
GPIO(FLASH_DSC_OVERRIDE, PIN(65), GPIO_OUT_HIGH) /* Empty */
GPIO(NC_051, PIN(51), GPIO_INPUT | GPIO_PULL_UP)
GPIO(CPU_PROCHOT, PIN(52), GPIO_OUT_LOW)
GPIO(ENABLE_TOUCHPAD, PIN(53), GPIO_OUT_LOW)
GPIO(SUSLED_L, PIN(127), GPIO_OUT_LOW)
GPIO(PD_RST_L, PIN(130), GPIO_ODR_HIGH)
GPIO(WLAN_OFF_L, PIN(132), GPIO_OUT_HIGH) /* Empty */
GPIO(PWRLED_L, PIN(133), GPIO_OUT_LOW)
/* RCIN# line to PCH for 8042 emulation */
GPIO(PCH_RCIN_L, PIN(135), GPIO_ODR_HIGH)
GPIO(LDO_EN, PIN(211), GPIO_OUT_LOW)
GPIO(NC_145, PIN(145), GPIO_INPUT | GPIO_PULL_UP)
GPIO(NC_147, PIN(147), GPIO_INPUT | GPIO_PULL_UP)
GPIO(USB2_OTG_ID, PIN(13), GPIO_ODR_LOW) /* Empty */
GPIO(NC_031, PIN(31), GPIO_INPUT | GPIO_PULL_UP)
GPIO(USB1_ENABLE, PIN(36), GPIO_OUT_HIGH)
GPIO(ENTERING_RW, PIN(41), GPIO_OUT_LOW)
GPIO(PCH_PWRBTN_L, PIN(45), GPIO_OUT_HIGH)
GPIO(BAT_PRESENT_L, PIN(56), GPIO_INPUT)
GPIO(USB_PD_WAKE, PIN(60), GPIO_OUT_LOW) /* Empty */
GPIO(PCH_WAKE_L, PIN(66), GPIO_ODR_HIGH)
GPIO(USB2_OTG_VBUSSENSE, PIN(105), GPIO_OUT_LOW) /* Empty */
GPIO(PCH_ACOK, PIN(110), GPIO_OUT_LOW)
GPIO(USB2_ENABLE, PIN(67), GPIO_OUT_HIGH)
/* Puesdo G3 */
GPIO(G3_SLEEP_EN, PIN(55), GPIO_OUT_LOW)
GPIO(NC_210, PIN(210), GPIO_INPUT | GPIO_PULL_UP)
/* I2C pins - these will be reconfigured for alternate function below */
GPIO(I2C0_0_SCL, PIN(15), GPIO_INPUT)
GPIO(I2C0_0_SDA, PIN(16), GPIO_INPUT)
GPIO(I2C0_1_SCL, PIN(134), GPIO_INPUT)
GPIO(I2C0_1_SDA, PIN(17), GPIO_INPUT)
GPIO(I2C1_SCL, PIN(22), GPIO_INPUT)
GPIO(I2C1_SDA, PIN(23), GPIO_INPUT)
GPIO(NC_20, PIN(20), GPIO_INPUT | GPIO_PULL_UP) /* I2C2_SCL */
GPIO(NC_21, PIN(21), GPIO_INPUT | GPIO_PULL_UP) /* I2C2_SDA */
GPIO(I2C3_SCL, PIN(24), GPIO_INPUT)
GPIO(I2C3_SDA, PIN(25), GPIO_INPUT)
/* prochot input from devices */
GPIO(PLATFORM_EC_PROCHOT, PIN(151), GPIO_INPUT) /* Empty */
GPIO(USB_C0_5V_EN, PIN(154), GPIO_OUT_LOW)
GPIO(CHARGE_LED1, PIN(155), GPIO_OUT_HIGH)
GPIO(CHARGE_LED2, PIN(156), GPIO_OUT_HIGH)
GPIO(A5_EN_C0, PIN(157), GPIO_OUT_LOW) /* Empty */
GPIO(FAN_PWR_DIS_L, PIN(160), GPIO_OUT_HIGH)
GPIO(NC_161, PIN(161), GPIO_INPUT | GPIO_PULL_UP)
GPIO(PCH_RTCRST_L, PIN(163), GPIO_ODR_HIGH) /* Empty */
GPIO(NC_123, PIN(123), GPIO_INPUT | GPIO_PULL_UP)
GPIO(ENABLE_BACKLIGHT, PIN(202), GPIO_OUT_HIGH)
GPIO(PMIC_SLP_SUS_L, PIN(201), GPIO_OUT_LOW)
GPIO(EN_PWR_WIFI, PIN(203), GPIO_OUT_HIGH) /* Empty */
GPIO(NC_204, PIN(204), GPIO_INPUT | GPIO_PULL_UP)
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH) /* SPI */
GPIO(USB_C0_CHARGE_EN_L, PIN(64), GPIO_OUT_LOW)
GPIO(NC_150, PIN(150), GPIO_INPUT | GPIO_PULL_UP)
GPIO(KBD_KSO2, PIN(101), GPIO_OUT_LOW) /* KB */
/* Alternate functions GPIO definitions */
/* LPC pins */
/* LPC_CLK_RUN_L - GPIO014 */
ALTERNATE(PIN_MASK(1, 0x10), 1, MODULE_LPC, 0)
/* LAD[0:3] - GPIO111-GPIO114, SERIRQ - GPIO115, PCI_CLK - GPIO117 */
ALTERNATE(PIN_MASK(11, 0xbe), 1, MODULE_LPC, 0)
/* LRESET# - GPIO116 */
ALTERNATE(PIN_MASK(11, 0x40), 1, MODULE_LPC, GPIO_INT_BOTH)
/* LFRAME# - GPIO120 */
ALTERNATE(PIN_MASK(12, 0x01), 1, MODULE_LPC, 0)
/* KB pins */
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP)
#define GPIO_KB_OUTPUT (GPIO_ODR_HIGH)
/* KB ROW - GPIO000-GPIO005 */
ALTERNATE(PIN_MASK(0, 0x3f), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB ROW - GPIO100-GPIO104, GPIO106-GPIO107 */
/* NOTE - GP101 should be configured as GPIO */
ALTERNATE(PIN_MASK(10, 0xdd), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT)
/* KB COL - GPIO032 */
ALTERNATE(PIN_MASK(3, 0x04), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO040, GPIO042-GPIO043 */
ALTERNATE(PIN_MASK(4, 0x0d), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO125-GPIO126 */
ALTERNATE(PIN_MASK(12, 0x60), 2, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* KB COL - GPIO142, GPIO144 */
ALTERNATE(PIN_MASK(14, 0x14), 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT)
/* VCC1_RST# - GPIO131 */
ALTERNATE(PIN_MASK(13, 0x02), 1, MODULE_PMU, 0)
/* nRESET_OUT - GPIO121 */
ALTERNATE(PIN_MASK(12, 0x02), 1, MODULE_PMU, 0)
/* GPIO162(UART_RX), GPIO165(UART_TX) */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* RPM-PWM for FAN */
/* TACH2PWM_IN - GPIO140 */
ALTERNATE(PIN_MASK(14, 0x01), 3, MODULE_PWM, 0)
/* TACH2PWM_OUT - GPIO034 */
ALTERNATE(PIN_MASK(3, 0x10), 3, MODULE_PWM, 0)
/* PWM for KBLight */
ALTERNATE(PIN_MASK(13, 0x40), 1, MODULE_PWM, 0) /* GP136 PWM1 */
/* ADC pins */
/* ADC1 - GPIO057 / PPVAR_BOOSTIN_SENSE */
ALTERNATE(PIN_MASK(5, 0x80), 1, MODULE_ADC, GPIO_ANALOG)
/* ADC3 - GPIO061 / IADP_ACMON_BMON. ADC4 - GPIO062 / PMON_PSYS */
ALTERNATE(PIN_MASK(6, 0x06), 1, MODULE_ADC, GPIO_ANALOG)
/* I2C pins */
/* I2C0_0 CLK - GPIO015, I2C0_0 DAT - GPIO016, I2C0_1 DAT - GPIO017 */
ALTERNATE(PIN_MASK(1, 0xe0), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C{1,2,3} CLK / DAT - GPIO022-GPIO025*/
ALTERNATE(PIN_MASK(2, 0x3c), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* I2C0_1 CLK - GPIO134 */
ALTERNATE(PIN_MASK(13, 0x10), 2, MODULE_I2C, GPIO_ODR_HIGH)
/* SPI pins */
/* MOSI - GPIO054 */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
/* MISO - GPIO164 */
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0)
/* PVT_SCLK - GPIO153 */
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)

222
board/lars/led.c
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@@ -1,222 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Power and battery LED control for Lars.
*/
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "led_common.h"
#include "util.h"
/* LED signals */
#define GPIO_BAT_LED_BLUE GPIO_CHARGE_LED1
#define GPIO_BAT_LED_AMBER GPIO_CHARGE_LED2
#define GPIO_PWR_LED_BLUE GPIO_PWRLED_L
#define GPIO_PWR_LED_AMBER GPIO_SUSLED_L
#define CRITICAL_LOW_BATTERY_PERMILLAGE 71
#define LOW_BATTERY_PERMILLAGE 137
#define FULL_BATTERY_PERMILLAGE 937
#define LED_TOTAL_4SECS_TICKS 16
#define LED_TOTAL_2SECS_TICKS 8
#define LED_ON_1SEC_TICKS 4
#define LED_ON_2SECS_TICKS 8
/* LEDs are High Activity */
#define TURN_ON 1
#define TURN_OFF 0
enum led_color {
LED_OFF = 0,
LED_BLUE,
LED_AMBER,
LED_PINK,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
const enum ec_led_id supported_led_ids[] = {
EC_LED_ID_POWER_LED, EC_LED_ID_BATTERY_LED};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
static int lars_led_set_gpio(enum led_color color,
enum gpio_signal gpio_led_blue_l,
enum gpio_signal gpio_led_amber_l)
{
switch (color) {
case LED_OFF:
gpio_set_level(gpio_led_blue_l, TURN_OFF);
gpio_set_level(gpio_led_amber_l, TURN_OFF);
break;
case LED_BLUE:
gpio_set_level(gpio_led_blue_l, TURN_ON);
gpio_set_level(gpio_led_amber_l, TURN_OFF);
break;
case LED_AMBER:
gpio_set_level(gpio_led_blue_l, TURN_OFF);
gpio_set_level(gpio_led_amber_l, TURN_ON);
break;
case LED_PINK:
gpio_set_level(gpio_led_blue_l, TURN_ON);
gpio_set_level(gpio_led_amber_l, TURN_ON);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
static int lars_led_set_color_battery(enum led_color color)
{
return lars_led_set_gpio(color, GPIO_BAT_LED_BLUE, GPIO_BAT_LED_AMBER);
}
static int lars_led_set_color_power(enum led_color color)
{
return lars_led_set_gpio(color, GPIO_PWR_LED_BLUE, GPIO_PWR_LED_AMBER);
}
static int lars_led_set_color(enum ec_led_id led_id, enum led_color color)
{
int rv;
led_auto_control(led_id, 0);
switch (led_id) {
case EC_LED_ID_BATTERY_LED:
rv = lars_led_set_color_battery(color);
break;
case EC_LED_ID_POWER_LED:
rv = lars_led_set_color_power(color);
break;
default:
return EC_ERROR_UNKNOWN;
}
return rv;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
if (brightness[EC_LED_COLOR_BLUE] != 0 &&
brightness[EC_LED_COLOR_YELLOW] != 0)
lars_led_set_color(led_id, LED_PINK);
else if (brightness[EC_LED_COLOR_BLUE] != 0)
lars_led_set_color(led_id, LED_BLUE);
else if (brightness[EC_LED_COLOR_YELLOW] != 0)
lars_led_set_color(led_id, LED_AMBER);
else
lars_led_set_color(led_id, LED_OFF);
return EC_SUCCESS;
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
/* Ignoring led_id as both leds support the same colors */
brightness_range[EC_LED_COLOR_BLUE] = 1;
brightness_range[EC_LED_COLOR_YELLOW] = 1;
}
static void lars_led_set_power(void)
{
static int power_ticks;
static int previous_state_suspend;
power_ticks++;
if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_STANDBY)) {
/* Reset ticks if entering suspend so LED turns amber
* as soon as possible. */
if (!previous_state_suspend)
power_ticks = 0;
/* Blink once every four seconds. */
lars_led_set_color_power(
(power_ticks % LED_TOTAL_4SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
previous_state_suspend = 1;
return;
}
previous_state_suspend = 0;
if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
lars_led_set_color_power(LED_OFF);
else if (chipset_in_state(CHIPSET_STATE_ON))
lars_led_set_color_power(LED_BLUE);
}
static void lars_led_set_battery(void)
{
static int battery_ticks;
uint32_t chflags = charge_get_flags();
int remaining_capacity;
int full_charge_capacity;
int permillage;
battery_ticks++;
remaining_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_CAP);
full_charge_capacity = *(int *)host_get_memmap(EC_MEMMAP_BATT_LFCC);
permillage = !full_charge_capacity ? 0 :
(1000 * remaining_capacity) / full_charge_capacity;
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
/* Make the percentage approximate to UI shown */
lars_led_set_color_battery(permillage <
FULL_BATTERY_PERMILLAGE ? LED_AMBER : LED_BLUE);
break;
case PWR_STATE_CHARGE_NEAR_FULL:
lars_led_set_color_battery(LED_BLUE);
break;
case PWR_STATE_DISCHARGE:
/* Less than 3%, blink one second every two seconds */
if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
permillage <= CRITICAL_LOW_BATTERY_PERMILLAGE)
lars_led_set_color_battery(
(battery_ticks % LED_TOTAL_2SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
/* Less than 10%, blink one second every four seconds */
else if (!chipset_in_state(CHIPSET_STATE_ANY_OFF) &&
permillage <= LOW_BATTERY_PERMILLAGE)
lars_led_set_color_battery(
(battery_ticks % LED_TOTAL_4SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
else
lars_led_set_color_battery(LED_OFF);
break;
case PWR_STATE_ERROR:
lars_led_set_color_battery(
(battery_ticks % LED_TOTAL_2SECS_TICKS <
LED_ON_1SEC_TICKS) ? LED_AMBER : LED_OFF);
break;
case PWR_STATE_IDLE: /* External power connected in IDLE. */
if (chflags & CHARGE_FLAG_FORCE_IDLE)
lars_led_set_color_battery(
(battery_ticks % LED_TOTAL_4SECS_TICKS <
LED_ON_2SECS_TICKS) ? LED_BLUE : LED_AMBER);
else
lars_led_set_color_battery(LED_BLUE);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
/* Called by hook task every 250mSec */
static void led_tick(void)
{
if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
lars_led_set_power();
if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
lars_led_set_battery();
}
DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);

22
board/lars/lfw/gpio.inc
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@@ -1,22 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Minimal set of GPIOs needed for LFW loader
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
/* SPI PVT chip select */
GPIO(PVT_CS0, PIN(146), GPIO_ODR_HIGH)
/* Alternate functions GPIO definition */
/* UART */
ALTERNATE(PIN_MASK(16, 0x24), 1, MODULE_UART, 0)
/* SPI pins */
ALTERNATE(PIN_MASK(5, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(16, 0x10), 1, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(15, 0x08), 1, MODULE_SPI, 0)

383
board/lars/usb_pd_policy.c
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@@ -1,383 +0,0 @@
/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "atomic.h"
#include "charge_manager.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_mux.h"
#include "usb_pd.h"
#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\
PDO_FIXED_COMM_CAP)
/* TODO: fill in correct source and sink capabilities */
const uint32_t pd_src_pdo[] = {
PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS),
};
const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
const uint32_t pd_snk_pdo[] = {
PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
PDO_BATT(4750, 21000, 15000),
PDO_VAR(4750, 21000, 3000),
};
const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
int pd_is_valid_input_voltage(int mv)
{
return 1;
}
void pd_transition_voltage(int idx)
{
/* No-operation: we are always 5V */
}
int pd_set_power_supply_ready(int port)
{
/* Disable charging */
gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1);
/* Provide VBUS */
gpio_set_level(GPIO_USB_C0_5V_EN, 1);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
return EC_SUCCESS; /* we are ready */
}
void pd_power_supply_reset(int port)
{
/* Disable VBUS */
gpio_set_level(GPIO_USB_C0_5V_EN, 0);
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
void pd_set_input_current_limit(int port, uint32_t max_ma,
uint32_t supply_voltage)
{
#ifdef CONFIG_CHARGE_MANAGER
struct charge_port_info charge;
charge.current = max_ma;
charge.voltage = supply_voltage;
charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge);
#endif
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
void typec_set_input_current_limit(int port, uint32_t max_ma,
uint32_t supply_voltage)
{
#ifdef CONFIG_CHARGE_MANAGER
struct charge_port_info charge;
charge.current = max_ma;
charge.voltage = supply_voltage;
charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge);
#endif
/* notify host of power info change */
pd_send_host_event(PD_EVENT_POWER_CHANGE);
}
int pd_snk_is_vbus_provided(int port)
{
return !gpio_get_level(GPIO_USB_C0_VBUS_WAKE_L);
}
int pd_board_checks(void)
{
return EC_SUCCESS;
}
int pd_check_power_swap(int port)
{
/*
* Allow power swap as long as we are acting as a dual role device,
* otherwise assume our role is fixed (not in S0 or console command
* to fix our role).
*/
return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0;
}
int pd_check_data_swap(int port, int data_role)
{
/* Allow data swap if we are a UFP, otherwise don't allow */
return (data_role == PD_ROLE_UFP) ? 1 : 0;
}
void pd_execute_data_swap(int port, int data_role)
{
/* Do nothing */
}
void pd_check_pr_role(int port, int pr_role, int flags)
{
/*
* If partner is dual-role power and dualrole toggling is on, consider
* if a power swap is necessary.
*/
if ((flags & PD_FLAGS_PARTNER_DR_POWER) &&
pd_get_dual_role() == PD_DRP_TOGGLE_ON) {
/*
* If we are a sink and partner is not externally powered, then
* swap to become a source. If we are source and partner is
* externally powered, swap to become a sink.
*/
int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER;
if ((!partner_extpower && pr_role == PD_ROLE_SINK) ||
(partner_extpower && pr_role == PD_ROLE_SOURCE))
pd_request_power_swap(port);
}
}
void pd_check_dr_role(int port, int dr_role, int flags)
{
/* If UFP, try to switch to DFP */
if ((flags & PD_FLAGS_PARTNER_DR_DATA) && dr_role == PD_ROLE_UFP)
pd_request_data_swap(port);
}
/* ----------------- Vendor Defined Messages ------------------ */
const struct svdm_response svdm_rsp = {
.identity = NULL,
.svids = NULL,
.modes = NULL,
};
int pd_custom_vdm(int port, int cnt, uint32_t *payload,
uint32_t **rpayload)
{
int cmd = PD_VDO_CMD(payload[0]);
uint16_t dev_id = 0;
int is_rw;
/* make sure we have some payload */
if (cnt == 0)
return 0;
switch (cmd) {
case VDO_CMD_VERSION:
/* guarantee last byte of payload is null character */
*(payload + cnt - 1) = 0;
CPRINTF("version: %s\n", (char *)(payload+1));
break;
case VDO_CMD_READ_INFO:
case VDO_CMD_SEND_INFO:
/* copy hash */
if (cnt == 7) {
dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
is_rw = VDO_INFO_IS_RW(payload[6]);
CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
HW_DEV_ID_MAJ(dev_id),
HW_DEV_ID_MIN(dev_id),
VDO_INFO_SW_DBG_VER(payload[6]),
is_rw);
} else if (cnt == 6) {
/* really old devices don't have last byte */
pd_dev_store_rw_hash(port, dev_id, payload + 1,
SYSTEM_IMAGE_UNKNOWN);
}
break;
case VDO_CMD_CURRENT:
CPRINTF("Current: %dmA\n", payload[1]);
break;
case VDO_CMD_FLIP:
usb_mux_flip(port);
break;
#ifdef CONFIG_USB_PD_LOGGING
case VDO_CMD_GET_LOG:
pd_log_recv_vdm(port, cnt, payload);
break;
#endif /* CONFIG_USB_PD_LOGGING */
}
return 0;
}
#ifdef CONFIG_USB_PD_ALT_MODE_DFP
static int dp_flags[CONFIG_USB_PD_PORT_COUNT];
/* DP Status VDM as returned by UFP */
static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT];
static void svdm_safe_dp_mode(int port)
{
/* make DP interface safe until configure */
dp_flags[port] = 0;
dp_status[port] = 0;
usb_mux_set(port, TYPEC_MUX_NONE,
USB_SWITCH_CONNECT, pd_get_polarity(port));
}
static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
{
/* Only enter mode if device is DFP_D capable */
if (mode_caps & MODE_DP_SNK) {
svdm_safe_dp_mode(port);
return 0;
}
return -1;
}
static int svdm_dp_status(int port, uint32_t *payload)
{
int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
CMD_DP_STATUS | VDO_OPOS(opos));
payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */
0, /* HPD level ... not applicable */
0, /* exit DP? ... no */
0, /* usb mode? ... no */
0, /* multi-function ... no */
(!!(dp_flags[port] & DP_FLAGS_DP_ON)),
0, /* power low? ... no */
(!!(dp_flags[port] & DP_FLAGS_DP_ON)));
return 2;
};
static int svdm_dp_config(int port, uint32_t *payload)
{
int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT);
int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]);
int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]);
if (!pin_mode)
return 0;
usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP,
USB_SWITCH_CONNECT, pd_get_polarity(port));
payload[0] = VDO(USB_SID_DISPLAYPORT, 1,
CMD_DP_CONFIG | VDO_OPOS(opos));
payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */
1, /* DPv1.3 signaling */
2); /* UFP connected */
return 2;
};
static void svdm_dp_post_config(int port)
{
dp_flags[port] |= DP_FLAGS_DP_ON;
if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING))
return;
gpio_set_level(GPIO_USB_C0_DP_HPD, 1);
}
static void hpd0_irq_deferred(void)
{
gpio_set_level(GPIO_USB_C0_DP_HPD, 1);
}
DECLARE_DEFERRED(hpd0_irq_deferred);
static int svdm_dp_attention(int port, uint32_t *payload)
{
int cur_lvl;
int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]);
int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]);
cur_lvl = gpio_get_level(GPIO_USB_C0_DP_HPD);
dp_status[port] = payload[1];
/* Its initial DP status message prior to config */
if (!(dp_flags[port] & DP_FLAGS_DP_ON)) {
if (lvl)
dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING;
return 1;
}
if (irq & cur_lvl) {
gpio_set_level(GPIO_USB_C0_DP_HPD, 0);
hook_call_deferred(&hpd0_irq_deferred_data,
HPD_DSTREAM_DEBOUNCE_IRQ);
} else if (irq & !cur_lvl) {
CPRINTF("ERR:HPD:IRQ&LOW\n");
return 0; /* nak */
} else {
gpio_set_level(GPIO_USB_C0_DP_HPD, lvl);
}
/* ack */
return 1;
}
static void svdm_exit_dp_mode(int port)
{
svdm_safe_dp_mode(port);
gpio_set_level(GPIO_USB_C0_DP_HPD, 0);
}
static int svdm_enter_gfu_mode(int port, uint32_t mode_caps)
{
/* Always enter GFU mode */
return 0;
}
static void svdm_exit_gfu_mode(int port)
{
}
static int svdm_gfu_status(int port, uint32_t *payload)
{
/*
* This is called after enter mode is successful, send unstructured
* VDM to read info.
*/
pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0);
return 0;
}
static int svdm_gfu_config(int port, uint32_t *payload)
{
return 0;
}
static int svdm_gfu_attention(int port, uint32_t *payload)
{
return 0;
}
const struct svdm_amode_fx supported_modes[] = {
{
.svid = USB_SID_DISPLAYPORT,
.enter = &svdm_enter_dp_mode,
.status = &svdm_dp_status,
.config = &svdm_dp_config,
.post_config = &svdm_dp_post_config,
.attention = &svdm_dp_attention,
.exit = &svdm_exit_dp_mode,
},
{
.svid = USB_VID_GOOGLE,
.enter = &svdm_enter_gfu_mode,
.status = &svdm_gfu_status,
.config = &svdm_gfu_config,
.attention = &svdm_gfu_attention,
.exit = &svdm_exit_gfu_mode,
}
};
const int supported_modes_cnt = ARRAY_SIZE(supported_modes);
#endif /* CONFIG_USB_PD_ALT_MODE_DFP */

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board/lars_pd/Makefile
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../../Makefile

151
board/lars_pd/board.c
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* lars_pd board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "i2c.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "usb_pd.h"
#include "usb_pd_tcpc.h"
#include "util.h"
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
/* Indicate which source is driving the ec_int line. */
static uint32_t ec_int_status;
static uint32_t pd_status_flags;
void pd_send_ec_int(void)
{
/* If any sources are active, then drive the line low */
gpio_set_level(GPIO_EC_INT, !ec_int_status);
}
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1 (C0 RX)
* Chan 3 : SPI1_TX (C0 TX)
* Chan 4 : TIM3_CH1 (C1 RX)
* Chan 5 : SPI2_TX (C1 TX)
*/
}
#include "gpio_list.h"
/* Initialize board. */
static void board_init(void)
{
/* Enable interrupts on VBUS transitions. */
gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
/* Set PD MCU system status bits */
if (system_jumped_to_this_image())
pd_status_flags |= PD_STATUS_JUMPED_TO_IMAGE;
if (system_get_image_copy() == SYSTEM_IMAGE_RW)
pd_status_flags |= PD_STATUS_IN_RW;
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/* ADC channels */
const struct adc_t adc_channels[] = {
/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
[ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
[ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"slave", I2C_PORT_SLAVE, 1000, GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA}
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
void tcpc_alert(int port)
{
/*
* This function is called when the TCPC sets one of
* bits in the Alert register and that bit's corresponding
* location in the Alert_Mask register is set.
*/
atomic_or(&ec_int_status, PD_STATUS_TCPC_ALERT_0);
pd_send_ec_int();
}
void tcpc_alert_clear(int port)
{
/*
* The TCPM has acknowledged all Alert bits and the
* Alert# line needs to be set inactive. Clear
* the corresponding port's bit in the static variable.
*/
atomic_clear(&ec_int_status, PD_STATUS_TCPC_ALERT_0);
pd_send_ec_int();
}
static void system_hibernate_deferred(void)
{
ccprintf("EC requested hibernate\n");
cflush();
system_hibernate(0, 0);
}
DECLARE_DEFERRED(system_hibernate_deferred);
/****************************************************************************/
/* Console commands */
static int command_ec_int(int argc, char **argv)
{
/* Indicate that ec_int gpio is active due to host command */
atomic_or(&ec_int_status, PD_STATUS_HOST_EVENT);
pd_send_ec_int();
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(ecint, command_ec_int,
"",
"Toggle EC interrupt line",
NULL);
static int ec_status_host_cmd(struct host_cmd_handler_args *args)
{
const struct ec_params_pd_status *p = args->params;
struct ec_response_pd_status *r = args->response;
/*
* ec_int_status is used to store state for HOST_EVENT,
* TCPC 0 Alert, and TCPC 1 Alert bits.
*/
r->status = ec_int_status | pd_status_flags;
args->response_size = sizeof(*r);
/* Have the PD follow the EC into hibernate. */
if (p->status & EC_STATUS_HIBERNATING)
hook_call_deferred(&system_hibernate_deferred_data, 0);
/*
* If the source of the EC int line was HOST_EVENT, it has
* been acknowledged so can always clear HOST_EVENT bit
* from the ec_int_status variable
*/
atomic_clear(&ec_int_status, PD_STATUS_HOST_EVENT);
return EC_RES_SUCCESS;
}
DECLARE_HOST_COMMAND(EC_CMD_PD_EXCHANGE_STATUS, ec_status_host_cmd,
EC_VER_MASK(EC_VER_PD_EXCHANGE_STATUS));

119
board/lars_pd/board.h
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* lars_pd board configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/*
* The console task is too big to include in both RO and RW images. Therefore,
* if the console task is defined, then only build an RW image. This can be
* useful for debugging to have a full console. Otherwise, without this task,
* a full RO and RW is built with a limited one-way output console.
*/
#ifdef HAS_TASK_CONSOLE
/*
* The flash size is only 32kB.
* No space for 2 partitions,
* put only RW at the beginning of the flash
*/
#undef CONFIG_FW_INCLUDE_RO
#undef CONFIG_RW_MEM_OFF
#define CONFIG_RW_MEM_OFF 0
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE 0
/* Fake full size if we had a RO partition */
#undef CONFIG_RW_SIZE
#define CONFIG_RW_SIZE CONFIG_FLASH_SIZE
#endif /* HAS_TASK_CONSOLE */
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* the UART console is on USART1 (PA9/PA10) */
#undef CONFIG_UART_CONSOLE
#define CONFIG_UART_CONSOLE 1
/* Optional features */
#define CONFIG_ADC
#undef CONFIG_ADC_WATCHDOG
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_COMMON_GPIO_SHORTNAMES
#undef CONFIG_DEBUG_ASSERT
#define CONFIG_FORCE_CONSOLE_RESUME
#define CONFIG_HIBERNATE
#define CONFIG_HIBERNATE_WAKEUP_PINS STM32_PWR_CSR_EWUP2
#undef CONFIG_HOSTCMD_EVENTS
#define CONFIG_HW_CRC
#define CONFIG_I2C
#define CONFIG_I2C_SLAVE
#undef CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LTO
#define CONFIG_STM_HWTIMER32
#undef CONFIG_TASK_PROFILING
#undef CONFIG_UART_TX_BUF_SIZE
#undef CONFIG_UART_TX_DMA
#undef CONFIG_UART_RX_DMA
#define CONFIG_UART_TX_BUF_SIZE 128
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_INTERNAL_COMP
#define CONFIG_USB_PD_PORT_COUNT 1
#define CONFIG_USB_PD_TCPC
#define CONFIG_USB_PD_TCPM_VBUS
#define CONFIG_USBC_VCONN
#define CONFIG_VBOOT_HASH
#define CONFIG_WATCHDOG
#undef CONFIG_WATCHDOG_HELP
#ifdef HAS_TASK_CONSOLE
#undef CONFIG_CONSOLE_HISTORY
#define CONFIG_CONSOLE_HISTORY 2
#else
#undef CONFIG_CONSOLE_CMDHELP
#define CONFIG_DEBUG_PRINTF
#define UARTN CONFIG_UART_CONSOLE
#define UARTN_BASE STM32_USART_BASE(CONFIG_UART_CONSOLE)
#endif /* HAS_TASK_CONSOLE */
/* Use PSTATE embedded in the RO image, not in its own erase block */
#undef CONFIG_FLASH_PSTATE_BANK
#undef CONFIG_FW_PSTATE_SIZE
#define CONFIG_FW_PSTATE_SIZE 0
/* I2C ports configuration */
#define I2C_PORT_SLAVE 0
#define I2C_PORT_EC I2C_PORT_SLAVE
/* slave address for host commands */
#ifdef HAS_TASK_HOSTCMD
#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR CONFIG_USB_PD_I2C_SLAVE_ADDR
#endif
#ifndef __ASSEMBLER__
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_ADC 3
#include "gpio_signal.h"
/* ADC signal */
enum adc_channel {
ADC_C0_CC1_PD = 0,
ADC_C0_CC2_PD,
/* Number of ADC channels */
ADC_CH_COUNT
};
/* 1.5A Rp */
#define PD_SRC_VNC PD_SRC_1_5_VNC_MV
#define PD_SRC_RD_THRESHOLD PD_SRC_1_5_RD_THRESH_MV
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

16
board/lars_pd/build.mk
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# -*- makefile -*-
# Copyright 2015 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F051C8T
CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f05x
board-y=board.o
# This target builds RW only. Therefore, remove RO from dependencies.
all_deps=$(patsubst ro,,$(def_all_deps))

23
board/lars_pd/ec.tasklist
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
/* TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) */ \
TASK_ALWAYS(PD_C0, pd_task, NULL, TASK_STACK_SIZE)

52
board/lars_pd/gpio.inc
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/* -*- mode:c -*-
*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
/* Interrupts */
GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(C, 14), GPIO_INT_BOTH, pd_vbus_evt_p0)
/* PD RX/TX */
GPIO(USB_C0_CC1_PD, PIN(A, 2), GPIO_ANALOG)
GPIO(USB_C_REF, PIN(A, 1), GPIO_ANALOG)
GPIO(USB_C0_CC2_PD, PIN(A, 4), GPIO_ANALOG)
GPIO(USB_C0_CC1_TX_DATA, PIN(B, 4), GPIO_INPUT)
GPIO(USB_C0_CC2_TX_DATA, PIN(A, 6), GPIO_INPUT)
GPIO(USB_PD_VBUS_WAKE, PIN(C, 13), GPIO_INPUT)
GPIO(PP3300_USB_PD_EN, PIN(A, 15), GPIO_OUT_HIGH)
GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1), GPIO_OUT_LOW)
GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2), GPIO_OUT_LOW)
GPIO(USB_C0_HOST_HIGH, PIN(A, 3), GPIO_OUT_LOW)
GPIO(USB_C0_CC1_ODL, PIN(A, 11), GPIO_ODR_LOW)
GPIO(USB_C0_CC2_ODL, PIN(A, 12), GPIO_ODR_LOW)
/*
* I2C pins should be configured as inputs until I2C module is
* initialized. This will avoid driving the lines unintentionally.
*/
GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT)
GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT)
GPIO(EC_INT, PIN(A, 14), GPIO_ODR_HIGH)
UNIMPLEMENTED(WP_L)
UNIMPLEMENTED(ENTERING_RW)
#if 0
/* Alternate functions */
GPIO(USB_C0_TX_CLKOUT, PIN(B, 8), GPIO_OUT_LOW)
GPIO(USB_C0_TX_CLKIN, PIN(B, 3), GPIO_OUT_LOW)
#endif
ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8 */
ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */
ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */

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board/lars_pd/usb_pd_config.h
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/* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "adc.h"
#include "chip/stm32/registers.h"
#include "gpio.h"
#include "ec_commands.h"
/* USB Power delivery board configuration */
#ifndef __CROS_EC_USB_PD_CONFIG_H
#define __CROS_EC_USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 16
#define TIM_CLOCK_PD_RX_C0 1
/* Timer channel */
#define TIM_TX_CCR_C0 1
#define TIM_RX_CCR_C0 1
#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
/* RX timer capture/compare register */
#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
#define TIM_RX_CCR_REG(p) (TIM_CCR_C0)
/* TX and RX timer register */
#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
#define TIM_REG_TX(p) (TIM_REG_TX_C0)
#define TIM_REG_RX(p) (TIM_REG_RX_C0)
/* use the hardware accelerator for CRC */
#define CONFIG_HW_CRC
/* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */
#define SPI_REGS(p) (STM32_SPI1_REGS)
static inline void spi_enable_clock(int port)
{
STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
}
/* DMA for transmit uses DMA CH3 for C0 */
#define DMAC_SPI_TX(p) (STM32_DMAC_CH3)
/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/
/* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */
#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM3_IC1
/* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */
#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
#define TIM_TX_CCR_IDX(p) (TIM_TX_CCR_C0)
#define TIM_RX_CCR_IDX(p) (TIM_RX_CCR_C0)
#define TIM_CCR_CS 1
/*
* EXTI line 21 is connected to the CMP1 output,
* EXTI line 22 is connected to the CMP2 output,
* C0 uses CMP2, and C1 uses CMP1.
*/
#define EXTI_COMP_MASK(p) (1 << 22)
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
/* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */
#define DMAC_TIM_RX(p) ( STM32_DMAC_CH2)
/* the pins used for communication need to be hi-speed */
static inline void pd_set_pins_speed(int port)
{
if (port == 0) {
/* 40 MHz pin speed on SPI PB3&4,
* (USB_C0_TX_CLKIN & USB_C0_CC1_TX_DATA)
*/
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000003C0;
/* 40 MHz pin speed on TIM16_CH1 (PB8),
* (USB_C0_TX_CLKOUT)
*/
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000;
}
}
/* Reset SPI peripheral used for TX */
static inline void pd_tx_spi_reset(int port)
{
if (port == 0) {
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
}
}
/* Drive the CC line from the TX block */
static inline void pd_tx_enable(int port, int polarity)
{
if (port == 0) {
/* put SPI function on TX pin */
if (polarity) {
/* USB_C0_CC2_TX_DATA: PA6 is SPI1 MISO */
gpio_set_alternate_function(GPIO_A, 0x0040, 0);
/* MCU ADC PA4 pin output low */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*4))) /* PA4 disable ADC */
| (1 << (2*4)); /* Set as GPO */
gpio_set_level(GPIO_USB_C0_CC2_PD, 0);
} else {
/* USB_C0_CC1_TX_DATA: PB4 is SPI1 MISO */
gpio_set_alternate_function(GPIO_B, 0x0010, 0);
/* MCU ADC PA2 pin output low */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*2))) /* PA2 disable ADC */
| (1 << (2*2)); /* Set as GPO */
gpio_set_level(GPIO_USB_C0_CC1_PD, 0);
}
}
}
/* Put the TX driver in Hi-Z state */
static inline void pd_tx_disable(int port, int polarity)
{
if (port == 0) {
if (polarity) {
/* Set TX_DATA to Hi-Z, PA6 is SPI1 MISO */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
& ~(3 << (2*6)));
/* set ADC PA4 pin to ADC function (Hi-Z) */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
| (3 << (2*4))); /* PA4 as ADC */
} else {
/* Set TX_DATA to Hi-Z, PB4 is SPI1 MISO */
STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
& ~(3 << (2*4)));
/* set ADC PA2 pin to ADC function (Hi-Z) */
STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
| (3 << (2*2))); /* PA2 as ADC */
}
}
}
/* we know the plug polarity, do the right configuration */
static inline void pd_select_polarity(int port, int polarity)
{
uint32_t val = STM32_COMP_CSR;
/* Use window mode so that COMP1 and COMP2 share non-inverting input */
val |= STM32_COMP_CMP1EN | STM32_COMP_CMP2EN | STM32_COMP_WNDWEN;
if (port == 0) {
/* C0 use the right comparator inverted input for COMP2 */
STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
(polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */
: STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
}
}
/* Initialize pins used for TX and put them in Hi-Z */
static inline void pd_tx_init(void)
{
gpio_config_module(MODULE_USB_PD, 1);
}
static inline void pd_set_host_mode(int port, int enable)
{
if (port == 0) {
if (enable) {
/* Pull up for host mode */
gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_OUTPUT);
gpio_set_level(GPIO_USB_C0_HOST_HIGH, 1);
/* High-Z is used for host mode. */
gpio_set_level(GPIO_USB_C0_CC1_ODL, 1);
gpio_set_level(GPIO_USB_C0_CC2_ODL, 1);
/* Set TX Hi-Z */
gpio_set_flags(GPIO_USB_C0_CC1_TX_DATA, GPIO_INPUT);
gpio_set_flags(GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
} else {
/* Set HOST_HIGH to High-Z for device mode. */
gpio_set_flags(GPIO_USB_C0_HOST_HIGH, GPIO_INPUT);
/* Pull low for device mode. */
gpio_set_level(GPIO_USB_C0_CC1_ODL, 0);
gpio_set_level(GPIO_USB_C0_CC2_ODL, 0);
}
}
}
/**
* Initialize various GPIOs and interfaces to safe state at start of pd_task.
*
* These include:
* VBUS, charge path based on power role.
* Physical layer CC transmit.
* VCONNs disabled.
*
* @param port USB-C port number
* @param power_role Power role of device
*/
static inline void pd_config_init(int port, uint8_t power_role)
{
/*
* Set CC pull resistors, and charge_en and vbus_en GPIOs to match
* the initial role.
*/
pd_set_host_mode(port, power_role);
/* Initialize TX pins and put them in Hi-Z */
pd_tx_init();
if (port == 0) {
gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0);
gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0);
}
}
static inline int pd_adc_read(int port, int cc)
{
return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD);
}
static inline void pd_set_vconn(int port, int polarity, int enable)
{
/* Set VCONN on the opposite CC line from the polarity */
if (port == 0) {
gpio_set_level(polarity ? GPIO_USB_C0_CC1_VCONN1_EN :
GPIO_USB_C0_CC2_VCONN1_EN, enable);
/* Set TX_DATA pin to Hi-Z */
gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA :
GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
}
}
#endif /* __CROS_EC_USB_PD_CONFIG_H */

4
test/build.mk
View File

@@ -19,9 +19,6 @@ test-list-$(BOARD_SAMUS)=
# Ryu has issues when building tests
test-list-$(BOARD_RYU)=
# Kunimitsu PD has issues when building tests
test-list-$(BOARD_KUNIMITSU_PD)=
# llama has issues when building tests
test-list-$(BOARD_LLAMA)=
@@ -30,7 +27,6 @@ test-list-$(BOARD_GLADOS_PD)=
test-list-$(BOARD_CHELL_PD)=
test-list-$(BOARD_OAK_PD)=
test-list-$(BOARD_SAMUS_PD)=
test-list-$(BOARD_LARS_PD)=
# Emulator tests
ifneq ($(TEST_LIST_HOST),)

6
util/flash_ec
View File

@@ -64,8 +64,6 @@ BOARDS_STM32=(
honeybuns
jerry
kitty
kunimitsu_pd
lars_pd
llama
lucid
minimuffin
@@ -114,8 +112,6 @@ BOARDS_NRF51=(
BOARDS_MEC1322=(
chell
glados
kunimitsu
lars
strago
)
@@ -333,7 +329,7 @@ function ec_uart() {
# Servo variables management
case "${BOARD}" in
oak_pd|samus_pd|strago_pd ) MCU="usbpd" ;;
chell_pd|glados_pd|kunimitsu_pd|lars_pd ) MCU="usbpd" ;;
chell_pd|glados_pd ) MCU="usbpd" ;;
dingdong|hoho|twinkie ) DUT_CONTROL_CMD="true" ; MCU="ec" ;;
*) MCU="ec" ;;
esac