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reef: Fix FAFT failure for firmware_ECUsbPorts
Modify USB enable GPIO name to comply with FAFT test. It uses this name format USB%d_ENABLE to power on/off all the USB ports. BRANCH=none BUG=none TEST=on Reef FAFT test firmware_ECUsbPorts passes Change-Id: I9b3b5d1668acfca5505dcff6708800f409555040 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/386854 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
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chrome-bot
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commit
5818cdc728
@@ -613,7 +613,7 @@ static void enable_input_devices(void)
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static void board_chipset_startup(void)
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{
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/* Enable USB-A port. */
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gpio_set_level(GPIO_EN_USB_A_5V, 1);
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gpio_set_level(GPIO_USB1_ENABLE, 1);
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hook_call_deferred(&enable_input_devices_data, 0);
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}
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@@ -639,7 +639,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, drive_sys_rst_odl_high, HOOK_PRIO_DEFAULT);
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static void board_chipset_shutdown(void)
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{
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/* Disable USB-A port. */
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gpio_set_level(GPIO_EN_USB_A_5V, 0);
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gpio_set_level(GPIO_USB1_ENABLE, 0);
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hook_call_deferred(&enable_input_devices_data, 0);
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/* FIXME(dhendrix): Drive USB_PD_RST_ODL low to prevent
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@@ -61,8 +61,8 @@
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/* USB-A config */
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#define CONFIG_USB_PORT_POWER_SMART
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#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
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#define GPIO_USB1_ENABLE GPIO_EN_USB_A_5V
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#define GPIO_USB2_ENABLE GPIO_EN_USB_A_5V
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#undef CONFIG_USB_PORT_POWER_SMART_PORT_COUNT
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#define CONFIG_USB_PORT_POWER_SMART_PORT_COUNT 1
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#define GPIO_USB_ILIM_SEL GPIO_USB_A_CHARGE_EN_L
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#define GPIO_USB_CTL1 GPIO_EN_PP5000
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@@ -131,7 +131,7 @@ GPIO(PCH_RCIN_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */
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GPIO(CHARGER_RST_ODL, PIN(C, 0), GPIO_ODR_HIGH)
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GPIO(USB_A_CHARGE_EN_L, PIN(4, 2), GPIO_OUT_HIGH)
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GPIO(EN_USB_TCPC_PWR, PIN(C, 3), GPIO_OUT_LOW)
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GPIO(EN_USB_A_5V, PIN(4, 1), GPIO_OUT_LOW)
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GPIO(USB1_ENABLE, PIN(4, 1), GPIO_OUT_LOW)
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GPIO(USB_C0_PD_RST_L, PIN(0, 3), GPIO_OUT_LOW) /* USB_C0_PD_RST_L */
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#if IS_PROTO == 0
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