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Add support for HW alerts
- Add a vendor command that provides alert counter. Userspace can use it e.g. for user metric analysis. - Add 'alerts' debug console command. It provides information about chip alerts: supported alerts, fuse status, interrupt status, alert counter. - Add 'alerts fire [INT]' command to fire a software defined alert (globalsec/fwN where N is 0,1,2,3). Signed-off-by: Anatol Pomazau <anatol@google.com> BUG=b:63523947 TEST=ran the FW at Pyro and checked alerts data sent to host Change-Id: I7cec0c451ed71076b44dad14a151b147ff1337e8 Reviewed-on: https://chromium-review.googlesource.com/817639 Commit-Ready: Anatol Pomazau <anatol@google.com> Tested-by: Anatol Pomazau <anatol@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This commit is contained in:
Anatol Pomazau
committed by
chrome-bot
chrome-bot
parent
760caca89b
commit
5a910a86be
@@ -360,4 +360,6 @@ enum nvmem_users {
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0xdb, 0xf4, 0x79, 0x5f, 0x8a, 0x0f, 0x28, 0x3f}
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#define CONFIG_RMA_AUTH_SERVER_KEY_ID 0x10
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#define CONFIG_ENABLE_H1_ALERTS
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#endif /* __CROS_EC_BOARD_H */
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364
chip/g/alerts.c
Normal file
364
chip/g/alerts.c
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@@ -0,0 +1,364 @@
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/* Copyright 2018 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "board_id.h"
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#include "common.h"
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#include "console.h"
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#include "endian.h"
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#include "extension.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "registers.h"
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#include "signed_header.h"
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#include "task.h"
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#include "tpm_vendor_cmds.h"
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#define BROM_FWBIT_APPLYSEC_SC300 0
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#define BROM_FWBIT_APPLYSEC_CAMO 1
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#define BROM_FWBIT_APPLYSEC_BUSERR 2
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#define BROM_FWBIT_APPLYSEC_BUSOBF 3
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#define BROM_FWBIT_APPLYSEC_HEARTBEAT 4
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#define BROM_FWBIT_APPLYSEC_BATMON 5
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#define BROM_FWBIT_APPLYSEC_RTCCHECK 6
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#define BROM_FWBIT_APPLYSEC_JITTERY 7
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#define BROM_FWBIT_APPLYSEC_TRNG 8
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#define BROM_FWBIT_APPLYSEC_VOLT 9
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#define BROM_FWBIT_APPLYSEC_NOB5 10
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#define BROM_FWBIT_APPLYSEC_UNKNOWN 11
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struct alert_desc {
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const char *name;
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const uint8_t fuse; // BROM_FWBIT_APPLYSEC_* fuse that gates the alert
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};
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// These numbers correspond to index at 'alert_counters/alert_descs' arrays
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#define ALERT_NUM_CAMO0_BREACH 0
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#define ALERT_NUM_CRYPTO0_DMEM_PARITY 1
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#define ALERT_NUM_CRYPTO0_DRF_PARITY 2
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#define ALERT_NUM_CRYPTO0_IMEM_PARITY 3
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#define ALERT_NUM_CRYPTO0_PGM_FAULT 4
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#define ALERT_NUM_DBCTRL_CPU0_D_IF_BUS_ERR 5
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#define ALERT_NUM_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG 6
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#define ALERT_NUM_DBCTRL_CPU0_I_IF_BUS_ERR 7
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#define ALERT_NUM_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG 8
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#define ALERT_NUM_DBCTRL_CPU0_S_IF_BUS_ERR 9
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#define ALERT_NUM_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG 10
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#define ALERT_NUM_DBCTRL_DDMA0_IF_BUS_ERR 11
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#define ALERT_NUM_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG 12
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#define ALERT_NUM_DBCTRL_DSPS0_IF_BUS_ERR 13
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#define ALERT_NUM_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG 14
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#define ALERT_NUM_DBCTRL_DUSB0_IF_BUS_ERR 15
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#define ALERT_NUM_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG 16
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#define ALERT_NUM_FUSE0_FUSE_DEFAULTS 17
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#define ALERT_NUM_GLOBALSEC_DIFF_FAIL 18
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#define ALERT_NUM_GLOBALSEC_FW0 19
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#define ALERT_NUM_GLOBALSEC_FW1 20
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#define ALERT_NUM_GLOBALSEC_FW2 21
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#define ALERT_NUM_GLOBALSEC_FW3 22
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#define ALERT_NUM_GLOBALSEC_HEARTBEAT_FAIL 23
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#define ALERT_NUM_GLOBALSEC_PROC_OPCODE_HASH 24
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#define ALERT_NUM_GLOBALSEC_SRAM_PARITY_SCRUB 25
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#define ALERT_NUM_KEYMGR0_AES_EXEC_CTR_MAX 26
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#define ALERT_NUM_KEYMGR0_AES_HKEY 27
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#define ALERT_NUM_KEYMGR0_CERT_LOOKUP 28
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#define ALERT_NUM_KEYMGR0_FLASH_ENTRY 29
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#define ALERT_NUM_KEYMGR0_PW 30
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#define ALERT_NUM_KEYMGR0_SHA_EXEC_CTR_MAX 31
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#define ALERT_NUM_KEYMGR0_SHA_FAULT 32
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#define ALERT_NUM_KEYMGR0_SHA_HKEY 33
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#define ALERT_NUM_PMU_BATTERY_MON 34
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#define ALERT_NUM_PMU_PMU_WDOG 35
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#define ALERT_NUM_RTC0_RTC_DEAD 36
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#define ALERT_NUM_TEMP0_MAX_TEMP 37
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#define ALERT_NUM_TEMP0_MAX_TEMP_DIFF 38
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#define ALERT_NUM_TEMP0_MIN_TEMP 39
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#define ALERT_NUM_TRNG0_OUT_OF_SPEC 40
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#define ALERT_NUM_TRNG0_TIMEOUT 41
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#define ALERT_NUM_VOLT0_VOLT_ERR 42
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#define ALERT_NUM_XO0_JITTERY_TRIM_DIS 43
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#define ALERTS_NUM 44
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uint16_t alert_counters[ALERTS_NUM];
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static void alerts_init(void)
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{
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int irq;
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// enable every single IRQ for globalsec alerts
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for (irq = GC_IRQNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT;
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irq <= GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT;
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irq++) {
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task_enable_irq(irq);
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}
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}
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DECLARE_HOOK(HOOK_INIT, alerts_init, HOOK_PRIO_DEFAULT);
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volatile uint32_t *INTR_STATUS_ADDR[] = {
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GREG32_ADDR(GLOBALSEC, ALERT_INTR_STS0),
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GREG32_ADDR(GLOBALSEC, ALERT_INTR_STS1),
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};
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BUILD_ASSERT(ARRAY_SIZE(INTR_STATUS_ADDR) * 32 >= ALERTS_NUM);
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static void alert_intr_clear(int alert)
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{
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int reg = alert / 32;
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int offset = alert % 32;
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*INTR_STATUS_ADDR[reg] = 1 << offset;
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}
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static void alert_interrupt_process(int alert)
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{
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alert_counters[alert]++;
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alert_intr_clear(alert);
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}
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#define GLOBALSEC_ALERT_COUNTER(name) \
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DECLARE_IRQ(GC_IRQNUM_GLOBALSEC_##name##_ALERT_INT, handler_##name, 1); \
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void handler_##name(void) \
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{ \
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alert_interrupt_process(ALERT_NUM_##name); \
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}
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GLOBALSEC_ALERT_COUNTER(CAMO0_BREACH);
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GLOBALSEC_ALERT_COUNTER(CRYPTO0_DMEM_PARITY);
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GLOBALSEC_ALERT_COUNTER(CRYPTO0_DRF_PARITY);
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GLOBALSEC_ALERT_COUNTER(CRYPTO0_IMEM_PARITY);
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GLOBALSEC_ALERT_COUNTER(CRYPTO0_PGM_FAULT);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_D_IF_BUS_ERR);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_I_IF_BUS_ERR);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_S_IF_BUS_ERR);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_DDMA0_IF_BUS_ERR);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_DDMA0_IF_UPDATE_WATCHDOG);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_DSPS0_IF_BUS_ERR);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_DSPS0_IF_UPDATE_WATCHDOG);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_DUSB0_IF_BUS_ERR);
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GLOBALSEC_ALERT_COUNTER(DBCTRL_DUSB0_IF_UPDATE_WATCHDOG);
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GLOBALSEC_ALERT_COUNTER(FUSE0_FUSE_DEFAULTS);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_DIFF_FAIL);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW0);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW1);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW2);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW3);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_HEARTBEAT_FAIL);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_PROC_OPCODE_HASH);
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GLOBALSEC_ALERT_COUNTER(GLOBALSEC_SRAM_PARITY_SCRUB);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_AES_EXEC_CTR_MAX);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_AES_HKEY);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_CERT_LOOKUP);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_FLASH_ENTRY);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_PW);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_SHA_EXEC_CTR_MAX);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_SHA_FAULT);
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GLOBALSEC_ALERT_COUNTER(KEYMGR0_SHA_HKEY);
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GLOBALSEC_ALERT_COUNTER(PMU_BATTERY_MON);
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GLOBALSEC_ALERT_COUNTER(PMU_PMU_WDOG);
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GLOBALSEC_ALERT_COUNTER(RTC0_RTC_DEAD);
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GLOBALSEC_ALERT_COUNTER(TEMP0_MAX_TEMP);
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GLOBALSEC_ALERT_COUNTER(TEMP0_MAX_TEMP_DIFF);
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GLOBALSEC_ALERT_COUNTER(TEMP0_MIN_TEMP);
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GLOBALSEC_ALERT_COUNTER(TRNG0_OUT_OF_SPEC);
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GLOBALSEC_ALERT_COUNTER(TRNG0_TIMEOUT);
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GLOBALSEC_ALERT_COUNTER(VOLT0_VOLT_ERR);
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GLOBALSEC_ALERT_COUNTER(XO0_JITTERY_TRIM_DIS);
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#define ALERTS_FORMAT_HAVEN 1
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struct vc_alerts_data {
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uint16_t version_id;
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uint16_t alerts_num;
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uint16_t counters[ALERTS_NUM];
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} __packed;
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static enum vendor_cmd_rc vc_get_alerts_data(enum vendor_cmd_cc code,
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void *buf, size_t input_size, size_t *response_size)
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{
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int i;
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struct vc_alerts_data *resp = buf;
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if (sizeof(struct vc_alerts_data) > *response_size)
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return VENDOR_RC_RESPONSE_TOO_BIG;
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memset(resp, 0, sizeof(struct vc_alerts_data));
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resp->version_id = htobe16(ALERTS_FORMAT_HAVEN);
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resp->alerts_num = htobe16(ALERTS_NUM);
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for (i = 0; i < ALERTS_NUM; i++) {
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// Most of alert_counters[i] will be zero. We want to avoid
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// disabling IRQ thus check counters with IRQ enabled.
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if (alert_counters[i]) {
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interrupt_disable();
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resp->counters[i] = htobe16(alert_counters[i]);
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alert_counters[i] = 0;
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interrupt_enable();
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}
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}
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*response_size = sizeof(struct vc_alerts_data);
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return VENDOR_RC_SUCCESS;
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}
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DECLARE_VENDOR_COMMAND(VENDOR_CC_GET_ALERTS_DATA, vc_get_alerts_data);
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#ifdef CONFIG_ENABLE_H1_ALERTS_CONSOLE
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const struct alert_desc alert_descs[] = {
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{ "camo0/breach", BROM_FWBIT_APPLYSEC_CAMO },
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{ "crypto0/dmem_parity", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "crypto0/drf_parity", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "crypto0/imem_parity", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "crypto0/pgm_fault", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "dbctrl_cpu0_D_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
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{ "dbctrl_cpu0_D_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
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{ "dbctrl_cpu0_I_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
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{ "dbctrl_cpu0_I_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
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{ "dbctrl_cpu0_S_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
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{ "dbctrl_cpu0_S_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
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{ "dbctrl_ddma0_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
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{ "dbctrl_ddma0_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
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{ "dbctrl_dsps0_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
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{ "dbctrl_dsps0_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
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{ "dbctrl_dusb0_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
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{ "dbctrl_dusb0_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
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{ "fuse0/fuse_defaults", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "globalsec/diff_fail", BROM_FWBIT_APPLYSEC_HEARTBEAT },
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{ "globalsec/fw0", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "globalsec/fw1", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "globalsec/fw2", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "globalsec/fw3", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "globalsec/heartbeat_fail", BROM_FWBIT_APPLYSEC_HEARTBEAT },
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{ "globalsec/proc_opcode_hash", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "globalsec/sram_parity_scrub", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/aes_exec_ctr_max", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/aes_hkey", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/cert_lookup", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/flash_entry", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/pw", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/sha_exec_ctr_max", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/sha_fault", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "keymgr0/sha_hkey", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "pmu/battery_mon", BROM_FWBIT_APPLYSEC_BATMON },
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{ "pmu/pmu_wdog", BROM_FWBIT_APPLYSEC_HEARTBEAT },
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{ "rtc0/rtc_dead", BROM_FWBIT_APPLYSEC_RTCCHECK },
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{ "temp0/max_temp", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "temp0/max_temp_diff", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "temp0/min_temp", BROM_FWBIT_APPLYSEC_UNKNOWN },
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{ "trng0/out_of_spec", BROM_FWBIT_APPLYSEC_TRNG },
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{ "trng0/timeout", BROM_FWBIT_APPLYSEC_TRNG },
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{ "volt0/volt_err", BROM_FWBIT_APPLYSEC_VOLT },
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{ "xo0/jittery_trim_dis", BROM_FWBIT_APPLYSEC_JITTERY },
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};
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BUILD_ASSERT(ARRAY_SIZE(alert_descs) == ALERTS_NUM);
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static int alert_intr_status(int alert)
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{
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int reg = alert / 32;
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int offset = alert % 32;
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return !!(*INTR_STATUS_ADDR[reg] & (1 << offset));
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}
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#ifdef CONFIG_BOARD_ID_SUPPORT
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static uint32_t fuse_enabled(void)
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{
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uint32_t fuses = GR_FUSE(FW_DEFINED_BROM_APPLYSEC);
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// get_current_image_header() is defined in board_id.c and available
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// only when CONFIG_BOARD_ID_SUPPORT is enabled
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const struct SignedHeader *hdr = get_current_image_header();
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return fuses & hdr->applysec_;
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}
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#else /* CONFIG_BOARD_ID_SUPPORT */
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static uint32_t fuse_enabled(void)
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{
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return GR_FUSE(FW_DEFINED_BROM_APPLYSEC);
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}
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#endif /* CONFIG_BOARD_ID_SUPPORT */
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static void command_alerts_list(void)
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{
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int i;
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uint32_t fuses = fuse_enabled();
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ccprintf("Globalsec alerts status\nColumns:\n"
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" * name\n"
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" * fuse state: '?' - not defined, '#' disabled, '+' enabled\n"
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" * interrupt state\n"
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" * alert counter\n");
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for (i = 0; i < ALERTS_NUM; i++) {
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const char *name = alert_descs[i].name;
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char fuse_status;
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int status = alert_intr_status(i);
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int8_t fuse = alert_descs[i].fuse;
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if (fuse == BROM_FWBIT_APPLYSEC_UNKNOWN)
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fuse_status = '?';
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else if (fuses & (1 << fuse))
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fuse_status = '+';
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else
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fuse_status = '#';
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ccprintf("%32s %c %d %d\n", name, fuse_status, status,
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alert_counters[i]);
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cflush();
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}
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}
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/* Fire a software enabled alert */
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static void command_alerts_fire(int interrupt)
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{
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int i = 0;
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int value = 0;
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for (i = 3; i >= 0; i--) {
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/* Trigger register consists of four 2-bit fields.
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* pair 01 triggers the alerts, pair 10 does not trigger
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*/
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value <<= 2;
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value |= (i == interrupt) ? 1 : 2;
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}
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GWRITE(GLOBALSEC, ALERT_FW_TRIGGER, value); // firing FW-N irq
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GWRITE(GLOBALSEC, ALERT_FW_TRIGGER, 0xaa); // back to normal
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}
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static int command_alerts(int argc, char **argv)
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{
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char *e;
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if (argc == 1) {
|
||||
command_alerts_list();
|
||||
return EC_SUCCESS;
|
||||
}
|
||||
|
||||
if (argc == 3) {
|
||||
if (!strcasecmp(argv[1], "fire")) {
|
||||
int alert = strtoi(argv[2], &e, 10);
|
||||
|
||||
if (*e || alert < 0 || alert > 3) {
|
||||
ccprintf("interrupt number must be in range "
|
||||
"[0..3]\n");
|
||||
return EC_ERROR_PARAM2;
|
||||
}
|
||||
|
||||
command_alerts_fire(alert);
|
||||
return EC_SUCCESS;
|
||||
}
|
||||
|
||||
return EC_ERROR_PARAM1;
|
||||
}
|
||||
|
||||
return EC_ERROR_PARAM_COUNT;
|
||||
}
|
||||
|
||||
DECLARE_CONSOLE_COMMAND(alerts, command_alerts,
|
||||
"<|fire [INT]>",
|
||||
"View/change alerts status");
|
||||
|
||||
#endif /* CONFIG_ENABLE_H1_ALERTS_CONSOLE */
|
||||
@@ -46,6 +46,11 @@ uint32_t check_board_id_vs_header(const struct board_id *id,
|
||||
*/
|
||||
int read_board_id(struct board_id *id);
|
||||
|
||||
/**
|
||||
* Return the image header for the current image copy
|
||||
*/
|
||||
const struct SignedHeader *get_current_image_header(void);
|
||||
|
||||
/**
|
||||
* Check if board ID in the image matches board ID field in the INFO1.
|
||||
*
|
||||
|
||||
@@ -67,6 +67,7 @@ chip-y+= jitter.o
|
||||
chip-y+= pmu.o
|
||||
chip-y+= trng.o
|
||||
chip-y+= runlevel.o
|
||||
chip-$(CONFIG_ENABLE_H1_ALERTS)+= alerts.o
|
||||
chip-$(CONFIG_USB_FW_UPDATE)+= usb_upgrade.o
|
||||
chip-$(CONFIG_NON_HC_FW_UPDATE)+= upgrade_fw.o post_reset.o upgrade.o
|
||||
chip-$(CONFIG_SPS)+= sps.o
|
||||
|
||||
@@ -968,6 +968,16 @@
|
||||
*/
|
||||
#undef CONFIG_IGNORE_G_UPDATE_CHECKS
|
||||
|
||||
/*
|
||||
* When enabled hardware alerts statistics provided via VendorCommand extension.
|
||||
*/
|
||||
#undef CONFIG_ENABLE_H1_ALERTS
|
||||
|
||||
/*
|
||||
* Enable console shell command 'alerts' that prints chip alerts statistics.
|
||||
*/
|
||||
#undef CONFIG_ENABLE_H1_ALERTS_CONSOLE
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
* Debugging config
|
||||
|
||||
@@ -50,6 +50,7 @@ enum vendor_cmd_cc {
|
||||
VENDOR_CC_DISABLE_RMA = 32,
|
||||
VENDOR_CC_MANAGE_CCD_PWD = 33,
|
||||
VENDOR_CC_CCD = 34,
|
||||
VENDOR_CC_GET_ALERTS_DATA = 35,
|
||||
|
||||
LAST_VENDOR_COMMAND = 65535,
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user