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stm32: Clean up SPI register usage

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Bitfields are now in registers.h where they belong.

BUG=chrome-os-partner:20529
BRANCH=none
TEST='crosec test' from u-boot still works

Change-Id: If0d79a66a90665c8ea336a006d76ccbc00a927ec
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60139
Reviewed-by: Vic Yang <victoryang@chromium.org>
This commit is contained in:
Randall Spangler
2013-06-26 14:43:12 -07:00
committed by ChromeBot
parent b3e0c66316
commit 5c82e77c19
2 changed files with 22 additions and 30 deletions
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25
chip/stm32/registers.h
View File

@@ -375,11 +375,12 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
#error Unsupported chip variant
#endif
/* Enable bits for RCC_APB/AHB regs */
/* Peripheral bits for RCC_APB/AHB regs */
#define STM32_RCC_PB1_USART2 (1 << 17)
#define STM32_RCC_PB1_USART3 (1 << 18)
#define STM32_RCC_PB1_USART4 (1 << 19)
#define STM32_RCC_PB1_USART5 (1 << 20)
#define STM32_RCC_PB2_SPI1 (1 << 12)
#define STM32_RCC_PB2_USART1 (1 << 14)
/* --- Watchdogs --- */
@@ -467,24 +468,28 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
/* The SPI controller registers */
struct stm32_spi_regs {
uint16_t ctrl1;
uint16_t cr1;
uint16_t _pad0;
uint16_t ctrl2;
uint16_t cr2;
uint16_t _pad1;
unsigned stat;
uint16_t data;
unsigned sr;
uint16_t dr;
uint16_t _pad2;
unsigned crcp;
unsigned rxcrc;
unsigned txcrc;
unsigned i2scfgr; /* STM32F10x only */
unsigned i2spr; /* STM32F10x only */
unsigned crcpr;
unsigned rxcrcr;
unsigned txcrcr;
unsigned i2scfgr; /* STM32F10x and STM32L only */
unsigned i2spr; /* STM32F10x and STM32L only */
};
/* Must be volatile, or compiler optimizes out repeated accesses */
typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
#define STM32_SPI1_REGS ((stm32_spi_regs_t *)STM32_SPI1_BASE)
#define STM32_SPI_CR1_SPE (1 << 6)
#define STM32_SPI_CR2_RXDMAEN (1 << 0)
#define STM32_SPI_CR2_TXDMAEN (1 << 1)
/* --- Debug --- */
#define STM32_DBGMCU_BASE 0xE0042000

27
chip/stm32/spi.c
View File

@@ -24,28 +24,15 @@
/* DMA channel option */
static const struct dma_option dma_tx_option = {
DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->data,
DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD
};
static const struct dma_option dma_rx_option = {
DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->data,
DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
DMA_MSIZE_BYTE | DMA_PSIZE_HALF_WORD
};
/* Status register flags that we use */
enum {
SR_RXNE = 1 << 0,
SR_TXE = 1 << 1,
SR_BSY = 1 << 7,
CR1_SPE = 1 << 6,
CR2_RXDMAEN = 1 << 0,
CR2_TXDMAEN = 1 << 1,
CR2_RXNEIE = 1 << 6,
};
/*
* Since message.c no longer supports our protocol, we must do it all here.
*
@@ -231,12 +218,12 @@ static void setup_for_transaction(void)
active = 0;
/* write 0xfd which will be our default output value */
spi->data = 0xfd;
spi->dr = 0xfd;
dma_disable(DMAC_SPI1_TX);
*in_msg = 0xff;
/* read a byte in case there is one, and the rx dma gets it */
dmac = spi->data;
dmac = spi->dr;
dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg);
}
@@ -423,13 +410,13 @@ static void spi_init(void)
STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;
/* Enable clocks to SPI1 module */
STM32_RCC_APB2ENR |= 1 << 12;
STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
/* Enable rx DMA and get ready to receive our first transaction */
spi->ctrl2 = CR2_RXDMAEN | CR2_TXDMAEN;
spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN;
/* Enable the SPI peripheral */
spi->ctrl1 |= CR1_SPE;
spi->cr1 |= STM32_SPI_CR1_SPE;
gpio_enable_interrupt(GPIO_SPI1_NSS);
}