mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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Lars: Remove second port of PD firmware
two port PD will keep interrupt low, and cause EC.PDCMD task stuck with exchange status loop before entering task-while-loop BUG=chrome-os-partner:48232 BRANCH=lars TEST=`make BOARD=lars -j`, OS can boot up normally Change-Id: I493c6d02170c731af430f28abf8ade38b47aff0f Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/315362 Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Ryan Zhang
@@ -53,7 +53,6 @@ static void board_init(void)
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{
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/* Enable interrupts on VBUS transitions. */
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gpio_enable_interrupt(GPIO_USB_C0_VBUS_WAKE_L);
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gpio_enable_interrupt(GPIO_USB_C1_VBUS_WAKE_L);
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/* Set PD MCU system status bits */
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if (system_jumped_to_this_image())
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@@ -66,10 +65,8 @@ DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
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/* ADC channels */
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const struct adc_t adc_channels[] = {
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/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
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[ADC_C1_CC1_PD] = {"C1_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
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[ADC_C0_CC1_PD] = {"C0_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
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[ADC_C0_CC2_PD] = {"C0_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
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[ADC_C1_CC2_PD] = {"C1_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
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};
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BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
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@@ -86,8 +83,7 @@ void tcpc_alert(int port)
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* bits in the Alert register and that bit's corresponding
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* location in the Alert_Mask register is set.
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*/
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atomic_or(&ec_int_status, port ?
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PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0);
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atomic_or(&ec_int_status, PD_STATUS_TCPC_ALERT_0);
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pd_send_ec_int();
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}
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@@ -98,8 +94,7 @@ void tcpc_alert_clear(int port)
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* Alert# line needs to be set inactive. Clear
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* the corresponding port's bit in the static variable.
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*/
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atomic_clear(&ec_int_status, port ?
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PD_STATUS_TCPC_ALERT_1 : PD_STATUS_TCPC_ALERT_0);
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atomic_clear(&ec_int_status, PD_STATUS_TCPC_ALERT_0);
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pd_send_ec_int();
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}
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@@ -61,7 +61,7 @@
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#define CONFIG_UART_TX_BUF_SIZE 128
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#define CONFIG_USB_PD_DUAL_ROLE
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#define CONFIG_USB_PD_INTERNAL_COMP
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#define CONFIG_USB_PD_PORT_COUNT 2
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#define CONFIG_USB_PD_PORT_COUNT 1
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#define CONFIG_USB_PD_TCPC
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#define CONFIG_USB_PD_TCPM_VBUS
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#define CONFIG_USBC_VCONN
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@@ -104,10 +104,8 @@
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/* ADC signal */
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enum adc_channel {
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ADC_C1_CC1_PD = 0,
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ADC_C0_CC1_PD,
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ADC_C0_CC1_PD = 0,
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ADC_C0_CC2_PD,
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ADC_C1_CC2_PD,
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/* Number of ADC channels */
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ADC_CH_COUNT
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};
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@@ -20,5 +20,4 @@
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TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
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/* TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) */ \
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TASK_ALWAYS(PD_C0, pd_task, NULL, TASK_STACK_SIZE) \
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TASK_ALWAYS(PD_C1, pd_task, NULL, TASK_STACK_SIZE)
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TASK_ALWAYS(PD_C0, pd_task, NULL, TASK_STACK_SIZE)
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@@ -7,33 +7,23 @@
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/* Interrupts */
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GPIO_INT(USB_C0_VBUS_WAKE_L, PIN(C, 14), GPIO_INT_BOTH, pd_vbus_evt_p0)
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GPIO_INT(USB_C1_VBUS_WAKE_L, PIN(C, 15), GPIO_INT_BOTH, pd_vbus_evt_p1)
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/* PD RX/TX */
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GPIO(USB_C0_CC1_PD, PIN(A, 2), GPIO_ANALOG)
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GPIO(USB_C_REF, PIN(A, 1), GPIO_ANALOG)
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GPIO(USB_C1_CC1_PD, PIN(A, 0), GPIO_ANALOG)
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GPIO(USB_C0_CC2_PD, PIN(A, 4), GPIO_ANALOG)
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GPIO(USB_C1_CC2_PD, PIN(A, 5), GPIO_ANALOG)
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GPIO(USB_C1_CCX_TX_DATA, PIN(B, 14), GPIO_INPUT)
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GPIO(USB_C0_CC1_TX_DATA, PIN(B, 4), GPIO_INPUT)
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GPIO(USB_C1_CC2_TX_SEL, PIN(B, 0), GPIO_OUT_LOW) /* C1_CC2_TX_SEL */
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GPIO(USB_C0_CC2_TX_DATA, PIN(A, 6), GPIO_INPUT)
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GPIO(USB_PD_VBUS_WAKE, PIN(C, 13), GPIO_INPUT)
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GPIO(PP3300_USB_PD_EN, PIN(A, 15), GPIO_OUT_HIGH)
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GPIO(USB_C0_CC1_VCONN1_EN, PIN(B, 1), GPIO_OUT_LOW)
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GPIO(USB_C0_CC2_VCONN1_EN, PIN(B, 2), GPIO_OUT_LOW)
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GPIO(USB_C1_CC1_VCONN1_EN, PIN(B, 9), GPIO_OUT_LOW)
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GPIO(USB_C1_CC2_VCONN1_EN, PIN(F, 0), GPIO_OUT_LOW)
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GPIO(USB_C0_HOST_HIGH, PIN(A, 3), GPIO_OUT_LOW)
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GPIO(USB_C1_HOST_HIGH, PIN(A, 7), GPIO_OUT_LOW)
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GPIO(USB_C0_CC1_ODL, PIN(A, 11), GPIO_ODR_LOW)
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GPIO(USB_C0_CC2_ODL, PIN(A, 12), GPIO_ODR_LOW)
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GPIO(USB_C1_CC1_ODL, PIN(B, 12), GPIO_ODR_LOW)
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GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW)
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/*
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* I2C pins should be configured as inputs until I2C module is
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@@ -42,26 +32,18 @@ GPIO(USB_C1_CC2_ODL, PIN(A, 8), GPIO_ODR_LOW)
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GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT)
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GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT)
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#ifdef BOARD_OAK_PD
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GPIO(EC_INT, PIN(B, 5), GPIO_OUT_HIGH)
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#else
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GPIO(EC_INT, PIN(A, 14), GPIO_OUT_HIGH)
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#endif
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UNIMPLEMENTED(WP_L)
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UNIMPLEMENTED(ENTERING_RW)
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#if 0
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/* Alternate functions */
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GPIO(USB_C1_TX_CLKOUT, PIN(B, 15), GPIO_OUT_LOW)
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GPIO(USB_C0_TX_CLKOUT, PIN(B, 8), GPIO_OUT_LOW)
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GPIO(USB_C1_TX_CLKIN, PIN(B, 13), GPIO_OUT_LOW)
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GPIO(USB_C0_TX_CLKIN, PIN(B, 3), GPIO_OUT_LOW)
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#endif
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ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
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ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */
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ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8 */
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ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15 */
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ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0) /* USART1: PA9/PA10 */
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ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */
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@@ -16,46 +16,36 @@
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/* Timer selection for baseband PD communication */
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#define TIM_CLOCK_PD_TX_C0 16
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#define TIM_CLOCK_PD_RX_C0 1
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#define TIM_CLOCK_PD_TX_C1 15
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#define TIM_CLOCK_PD_RX_C1 3
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/* Timer channel */
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#define TIM_TX_CCR_C0 1
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#define TIM_RX_CCR_C0 1
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#define TIM_TX_CCR_C1 2
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#define TIM_RX_CCR_C1 1
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#define TIM_CLOCK_PD_TX(p) ((p) ? TIM_CLOCK_PD_TX_C1 : TIM_CLOCK_PD_TX_C0)
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#define TIM_CLOCK_PD_RX(p) ((p) ? TIM_CLOCK_PD_RX_C1 : TIM_CLOCK_PD_RX_C0)
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#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
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#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
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/* RX timer capture/compare register */
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#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
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#define TIM_CCR_C1 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C1, TIM_RX_CCR_C1))
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#define TIM_RX_CCR_REG(p) ((p) ? TIM_CCR_C1 : TIM_CCR_C0)
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#define TIM_RX_CCR_REG(p) (TIM_CCR_C0)
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/* TX and RX timer register */
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#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
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#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
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#define TIM_REG_TX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C1))
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#define TIM_REG_RX_C1 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C1))
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#define TIM_REG_TX(p) ((p) ? TIM_REG_TX_C1 : TIM_REG_TX_C0)
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#define TIM_REG_RX(p) ((p) ? TIM_REG_RX_C1 : TIM_REG_RX_C0)
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#define TIM_REG_TX(p) (TIM_REG_TX_C0)
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#define TIM_REG_RX(p) (TIM_REG_RX_C0)
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/* use the hardware accelerator for CRC */
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#define CONFIG_HW_CRC
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/* TX uses SPI1 on PB3-4 for port C0, SPI2 on PB 13-14 for port C1 */
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#define SPI_REGS(p) ((p) ? STM32_SPI2_REGS : STM32_SPI1_REGS)
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#define SPI_REGS(p) (STM32_SPI1_REGS)
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static inline void spi_enable_clock(int port)
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{
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if (port == 0)
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STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
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else
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STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
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STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
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}
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/* DMA for transmit uses DMA CH3 for C0 and DMA_CH5 for C1 */
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#define DMAC_SPI_TX(p) ((p) ? STM32_DMAC_CH5 : STM32_DMAC_CH3)
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/* DMA for transmit uses DMA CH3 for C0 */
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#define DMAC_SPI_TX(p) (STM32_DMAC_CH3)
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/* RX uses COMP1 and TIM1 CH1 on port C0 and COMP2 and TIM3_CH1 for port C1*/
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/* C1 RX use CMP1, TIM3_CH1, DMA_CH4 */
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@@ -63,8 +53,8 @@ static inline void spi_enable_clock(int port)
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/* C0 RX use CMP2, TIM1_CH1, DMA_CH2 */
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#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
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#define TIM_TX_CCR_IDX(p) ((p) ? TIM_TX_CCR_C1 : TIM_TX_CCR_C0)
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#define TIM_RX_CCR_IDX(p) ((p) ? TIM_RX_CCR_C1 : TIM_RX_CCR_C0)
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#define TIM_TX_CCR_IDX(p) (TIM_TX_CCR_C0)
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#define TIM_RX_CCR_IDX(p) (TIM_RX_CCR_C0)
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#define TIM_CCR_CS 1
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/*
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@@ -72,14 +62,14 @@ static inline void spi_enable_clock(int port)
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* EXTI line 22 is connected to the CMP2 output,
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* C0 uses CMP2, and C1 uses CMP1.
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*/
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#define EXTI_COMP_MASK(p) ((p) ? (1<<21) : (1 << 22))
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#define EXTI_COMP_MASK(p) (1 << 22)
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#define IRQ_COMP STM32_IRQ_COMP
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/* triggers packet detection on comparator falling edge */
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#define EXTI_XTSR STM32_EXTI_FTSR
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/* DMA for receive uses DMA_CH2 for C0 and DMA_CH4 for C1 */
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#define DMAC_TIM_RX(p) ((p) ? STM32_DMAC_CH4 : STM32_DMAC_CH2)
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#define DMAC_TIM_RX(p) ( STM32_DMAC_CH2)
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/* the pins used for communication need to be hi-speed */
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static inline void pd_set_pins_speed(int port)
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@@ -93,13 +83,6 @@ static inline void pd_set_pins_speed(int port)
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* (USB_C0_TX_CLKOUT)
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*/
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00030000;
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} else {
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/* 40 MHz pin speed on SPI PB13/14,
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* (USB_C1_TX_CLKIN & USB_C1_CCX_TX_DATA)
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*/
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3C000000;
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/* 40 MHz pin speed on TIM15_CH2 (PB15) */
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0xC0000000;
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}
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}
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@@ -110,10 +93,6 @@ static inline void pd_tx_spi_reset(int port)
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/* Reset SPI1 */
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STM32_RCC_APB2RSTR |= (1 << 12);
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STM32_RCC_APB2RSTR &= ~(1 << 12);
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} else {
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/* Reset SPI2 */
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STM32_RCC_APB1RSTR |= (1 << 14);
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STM32_RCC_APB1RSTR &= ~(1 << 14);
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}
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}
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@@ -139,30 +118,6 @@ static inline void pd_tx_enable(int port, int polarity)
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| (1 << (2*2)); /* Set as GPO */
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gpio_set_level(GPIO_USB_C0_CC1_PD, 0);
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}
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} else {
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/* put SPI function on TX pin */
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/* USB_C1_CCX_TX_DATA: PB14 is SPI1 MISO */
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gpio_set_alternate_function(GPIO_B, 0x4000, 0);
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/* MCU ADC pin output low */
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if (polarity) {
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*5))) /* PA5 disable ADC */
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| (1 << (2*5)); /* Set as GPO */
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gpio_set_level(GPIO_USB_C1_CC2_PD, 0);
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} else {
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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& ~(3 << (2*0))) /* PA0 disable ADC */
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| (1 << (2*0)); /* Set as GPO */
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gpio_set_level(GPIO_USB_C1_CC1_PD, 0);
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}
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/*
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* There is a pin muxer to select CC1 or CC2 TX_DATA,
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* Pin mux is controlled by USB_C1_CC2_TX_SEL pin,
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* USB_C1_CC1_TX_DATA will be selected, if polarity is 0,
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* USB_C1_CC2_TX_DATA will be selected, if polarity is 1 .
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*/
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gpio_set_level(GPIO_USB_C1_CC2_TX_SEL, polarity);
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}
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}
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@@ -185,19 +140,6 @@ static inline void pd_tx_disable(int port, int polarity)
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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| (3 << (2*2))); /* PA2 as ADC */
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}
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} else {
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/* Set TX_DATA (PB14) Hi-Z */
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STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B)
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& ~(3 << (2*14)));
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if (polarity) {
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/* set ADC PA5 pin to ADC function (Hi-Z) */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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| (3 << (2*5))); /* PA5 as ADC */
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} else {
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/* set ADC PA0 pin to ADC function (Hi-Z) */
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STM32_GPIO_MODER(GPIO_A) = (STM32_GPIO_MODER(GPIO_A)
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| (3 << (2*0))); /* PA0 as ADC */
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}
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}
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}
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@@ -214,11 +156,6 @@ static inline void pd_select_polarity(int port, int polarity)
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STM32_COMP_CSR = (val & ~STM32_COMP_CMP2INSEL_MASK) |
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(polarity ? STM32_COMP_CMP2INSEL_INM4 /* PA4: C0_CC2 */
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: STM32_COMP_CMP2INSEL_INM6);/* PA2: C0_CC1 */
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} else {
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/* C1 use the right comparator inverted input for COMP1 */
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STM32_COMP_CSR = (val & ~STM32_COMP_CMP1INSEL_MASK) |
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(polarity ? STM32_COMP_CMP1INSEL_INM5 /* PA5: C1_CC2 */
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: STM32_COMP_CMP1INSEL_INM6);/* PA0: C1_CC1 */
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}
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}
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@@ -247,23 +184,6 @@ static inline void pd_set_host_mode(int port, int enable)
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gpio_set_level(GPIO_USB_C0_CC1_ODL, 0);
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gpio_set_level(GPIO_USB_C0_CC2_ODL, 0);
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}
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} else {
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if (enable) {
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/* Pull up for host mode */
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gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_OUTPUT);
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gpio_set_level(GPIO_USB_C1_HOST_HIGH, 1);
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/* High-Z is used for host mode. */
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gpio_set_level(GPIO_USB_C1_CC1_ODL, 1);
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gpio_set_level(GPIO_USB_C1_CC2_ODL, 1);
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/* Set TX Hi-Z */
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gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
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} else {
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/* Set HOST_HIGH to High-Z for device mode. */
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gpio_set_flags(GPIO_USB_C1_HOST_HIGH, GPIO_INPUT);
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/* Pull low for device mode. */
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gpio_set_level(GPIO_USB_C1_CC1_ODL, 0);
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gpio_set_level(GPIO_USB_C1_CC2_ODL, 0);
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}
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}
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}
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@@ -292,18 +212,12 @@ static inline void pd_config_init(int port, uint8_t power_role)
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if (port == 0) {
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gpio_set_level(GPIO_USB_C0_CC1_VCONN1_EN, 0);
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gpio_set_level(GPIO_USB_C0_CC2_VCONN1_EN, 0);
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} else {
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gpio_set_level(GPIO_USB_C1_CC1_VCONN1_EN, 0);
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gpio_set_level(GPIO_USB_C1_CC2_VCONN1_EN, 0);
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}
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}
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static inline int pd_adc_read(int port, int cc)
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{
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||||
if (port == 0)
|
||||
return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD);
|
||||
else
|
||||
return adc_read_channel(cc ? ADC_C1_CC2_PD : ADC_C1_CC1_PD);
|
||||
return adc_read_channel(cc ? ADC_C0_CC2_PD : ADC_C0_CC1_PD);
|
||||
}
|
||||
|
||||
static inline void pd_set_vconn(int port, int polarity, int enable)
|
||||
@@ -315,11 +229,6 @@ static inline void pd_set_vconn(int port, int polarity, int enable)
|
||||
/* Set TX_DATA pin to Hi-Z */
|
||||
gpio_set_flags(polarity ? GPIO_USB_C0_CC1_TX_DATA :
|
||||
GPIO_USB_C0_CC2_TX_DATA, GPIO_INPUT);
|
||||
} else {
|
||||
gpio_set_level(polarity ? GPIO_USB_C1_CC1_VCONN1_EN :
|
||||
GPIO_USB_C1_CC2_VCONN1_EN, enable);
|
||||
/* Set TX_DATA pin to Hi-Z */
|
||||
gpio_set_flags(GPIO_USB_C1_CCX_TX_DATA, GPIO_INPUT);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user