scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2026-01-09 17:11:42 +00:00
Code Issues Packages Projects Releases Wiki Activity

stm32f0: samus_pd: add hibernate and enable wake pins for samus

Browse Source 
Add hibernate functionality for stm32f0, and enable wake pins
for samus PD MCU. Samus wake pins are VBUS present on either port.

BUG=chrome-os-partner:31226
BRANCH=none
TEST=load onto samus PD. test hibernate console command:

> hibernate 0 500000
Hibernating for 0.500000 s
(5 seconds later)

--- UART initialized after reboot ---
[Reset cause: hibernate]
...
> hibernate
Hibernating until wake pin asserted.
(plug in AC)

--- UART initialized after reboot ---
[Reset cause: hibernate]

Change-Id: Ib86f2677721df29e7bf6975e239de79c25a38795
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219105
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Alec Berg
2014-09-19 13:48:56 -07:00
committed by chrome-internal-fetch
parent 9bebf41d16
commit 5e7c09ed3e
5 changed files with 41 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
board/samus_pd/board.h
View File

@@ -19,6 +19,7 @@
#define CONFIG_ADC
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_FORCE_CONSOLE_RESUME
#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP3|STM32_PWR_CSR_EWUP8)
#define CONFIG_HW_CRC
#define CONFIG_I2C
#undef CONFIG_LID_SWITCH

2
chip/stm32/clock-stm32f.c
View File

@@ -170,7 +170,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
asm volatile("cpsid i");
/* enable the wake up pin */
STM32_PWR_CSR |= (1<<8);
STM32_PWR_CSR |= STM32_PWR_CSR_EWUP;
STM32_PWR_CR |= 0xe;
CPU_SCB_SYSCTRL |= 0x4;
/* go to Standby mode */

24
chip/stm32/clock-stm32f0.c
View File

@@ -258,6 +258,30 @@ static void config_hispeed_clock(void)
#endif
}
void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
{
uint32_t rtc, rtcss;
if (seconds || microseconds)
set_rtc_alarm(seconds, microseconds, &rtc, &rtcss);
/* interrupts off now */
asm volatile("cpsid i");
#ifdef CONFIG_HIBERNATE_WAKEUP_PINS
/* enable the wake up pins */
STM32_PWR_CSR |= CONFIG_HIBERNATE_WAKEUP_PINS;
#endif
STM32_PWR_CR |= 0xe;
CPU_SCB_SYSCTRL |= 0x4;
/* go to Standby mode */
asm("wfi");
/* we should never reach that point */
while (1)
;
}
#ifdef CONFIG_LOW_POWER_IDLE
void clock_refresh_console_in_use(void)

12
chip/stm32/registers.h
View File

@@ -493,6 +493,18 @@ typedef volatile struct timer_ctlr timer_ctlr_t;
#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00)
#define STM32_PWR_CR_LPSDSR (1 << 0)
#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
#if defined(CHIP_FAMILY_STM32F)
#define STM32_PWR_CSR_EWUP (1 << 8)
#elif defined(CHIP_FAMILY_STM32F0)
#define STM32_PWR_CSR_EWUP1 (1 << 8)
#define STM32_PWR_CSR_EWUP2 (1 << 9)
#define STM32_PWR_CSR_EWUP3 (1 << 10)
#define STM32_PWR_CSR_EWUP4 (1 << 11)
#define STM32_PWR_CSR_EWUP5 (1 << 12)
#define STM32_PWR_CSR_EWUP6 (1 << 13)
#define STM32_PWR_CSR_EWUP7 (1 << 14)
#define STM32_PWR_CSR_EWUP8 (1 << 15)
#endif
#if defined(CHIP_FAMILY_STM32L)
#define STM32_RCC_BASE 0x40023800

3
include/config.h
View File

@@ -570,6 +570,9 @@
/* Enable system hibernate */
#define CONFIG_HIBERNATE
/* For ECs with multiple wakeup pins, define enabled wakeup pins */
#undef CONFIG_HIBERNATE_WAKEUP_PINS
/*****************************************************************************/
/* I2C configuration */