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stm32: flash: enable data and instruction cache properly

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The flash controller of STM32F4 and STM32L4 supports data and
instruction caching. Enable them properly.

BRANCH=none
BUG=b:38077127
TEST=on rose,
      > rw 0x40023c00
      read 0x40023c00 = 0x00000701

     Touch process loop is 5% faster.

Change-Id: Ibb28c0ed0c6a293547d5f0f7c6962f36fa417dd3
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/497230
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Wei-Ning Huang
2017-05-07 13:48:22 +08:00
committed by chrome-bot
parent ced1b4f90a
commit 5f523464bb
2 changed files with 19 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
chip/stm32/clock-f.c
View File

@@ -165,14 +165,30 @@ void clock_init(void)
* put 1 Wait-State for flash access to ensure proper reads at 48Mhz
* and enable prefetch buffer.
*/
/* Enable data and instruction cache. */
STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN;
#ifdef CHIP_FAMILY_STM32F4
/* Enable data and instruction cache. */
STM32_FLASH_ACR |= STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN;
#endif
config_hispeed_clock();
rtc_init();
}
#ifdef CHIP_FAMILY_STM32F4
void reset_flash_cache(void)
{
/* Disable data and instruction cache. */
STM32_FLASH_ACR &= ~(STM32_FLASH_ACR_DCEN | STM32_FLASH_ACR_ICEN);
/* Reset data and instruction cache */
STM32_FLASH_ACR |= STM32_FLASH_ACR_DCRST | STM32_FLASH_ACR_ICRST;
}
DECLARE_HOOK(HOOK_SYSJUMP, reset_flash_cache, HOOK_PRIO_DEFAULT);
#endif
/*****************************************************************************/
/* Console commands */

2
chip/stm32/registers.h
View File

@@ -1356,6 +1356,8 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
#define STM32_FLASH_ACR_PRFTEN (1 << 8)
#define STM32_FLASH_ACR_ICEN (1 << 9)
#define STM32_FLASH_ACR_DCEN (1 << 10)
#define STM32_FLASH_ACR_ICRST (1 << 11)
#define STM32_FLASH_ACR_DCRST (1 << 12)
#define STM32_FLASH_PDKEYR REG32(STM32_FLASH_REGS_BASE + 0x04)
#define STM32_FLASH_KEYR REG32(STM32_FLASH_REGS_BASE + 0x08)
#define FLASH_KEYR_KEY1 0x45670123