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Reduce LPC command parameters to 128 bytes; add LPC memory-mapped space

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This will allow more efficient access to EC-provided data (temperature,
fan, battery) by the main processor.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=chrome-os-partner:7857
TEST='ectool hello' from link main processor should still work

Change-Id: I2dc683f3441b34de9fb4debf772e386b9fdcfa82
This commit is contained in:
Randall Spangler
2012-02-15 15:05:35 -08:00
parent c160dae1d4
commit 6101cebb6a
4 changed files with 25 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
chip/lm4/lpc.c
View File

@@ -163,7 +163,13 @@ int lpc_init(void)
uint8_t *lpc_get_host_range(int slot)
{
return (uint8_t *)LPC_POOL_CMD_DATA + 256 * slot;
return (uint8_t *)LPC_POOL_CMD_DATA + EC_LPC_PARAM_SIZE * slot;
}
uint8_t *lpc_get_memmap_range(void)
{
return (uint8_t *)LPC_POOL_CMD_DATA + EC_LPC_PARAM_SIZE * 2;
}

6
include/lpc.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -27,6 +27,10 @@ int lpc_init(void);
* commands, 1 for usermode-originated commands. */
uint8_t *lpc_get_host_range(int slot);
/* Returns a pointer to the memory-mapped buffer. This buffer is writable at
* any time, and the host can read it at any time. */
uint8_t *lpc_get_memmap_range(void);
/* Sends a response to a host command. The bottom 4 bits of <status>
* are sent in the status byte. <slot> is 0 for kernel-originated
* commands, 1 for usermode-originated commands. */

15
include/lpc_commands.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -24,15 +24,18 @@
#define EC_LPC_ADDR_KERNEL_PARAM 0x800
#define EC_LPC_ADDR_USER_DATA 0x200
#define EC_LPC_ADDR_USER_CMD 0x204
#define EC_LPC_ADDR_USER_PARAM 0x900
#define EC_LPC_PARAM_SIZE 256 /* Size of param areas in bytes */
#define EC_LPC_ADDR_USER_PARAM 0x880
#define EC_LPC_PARAM_SIZE 128 /* Size of each param area in bytes */
#define EC_LPC_ADDR_MEMMAP 0x900
#define EC_LPC_MEMMAP_SIZE 256
/* LPC command status byte masks */
/* EC is busy processing a command. This covers both bit 0x04, which
* is the busy-bit, and 0x02, which is the bit which indicates the
* host has written a byte but the EC hasn't picked it up yet. */
#define EC_LPC_BUSY_MASK 0x06
#define EC_LPC_STATUS_MASK 0xF0 /* Mask for status codes in status byte */
#define EC_LPC_STATUS_MASK 0xf0 /* Mask for status codes in status byte */
#define EC_LPC_GET_STATUS(x) (((x) & EC_LPC_STATUS_MASK) >> 4)
/* LPC command response codes */
@@ -55,7 +58,7 @@ enum lpc_status {
* busy, because the reboot command is processed at interrupt
* level. Note that when the EC reboots, the host will reboot too, so
* there is no response to this command. */
#define EC_LPC_COMMAND_REBOOT 0xD1 /* Think "die" */
#define EC_LPC_COMMAND_REBOOT 0xd1 /* Think "die" */
/* Hello. This is a simple command to test the EC is responsive to
@@ -100,7 +103,7 @@ struct lpc_response_read_test {
/* Flash commands */
/* Maximum bytes that can be read/written in a single command */
#define EC_LPC_FLASH_SIZE_MAX 128
#define EC_LPC_FLASH_SIZE_MAX 64
/* Get flash info */
#define EC_LPC_COMMAND_FLASH_INFO 0x10

8
util/ectool.c
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
@@ -42,10 +42,10 @@ const char help_str[] =
" Set target fan RPM\n"
"\n"
"Not working for you? Make sure LPC I/O is configured:\n"
" pci_write32 0 0x1f 0 0x88 0x007c0801\n"
" pci_write32 0 0x1f 0 0x8c 0x007c0901\n"
" pci_write32 0 0x1f 0 0x88 0x00fc0801\n"
" pci_write32 0 0x1f 0 0x8c 0x00fc0901\n"
" pci_write16 0 0x1f 0 0x80 0x0010\n"
" pci_write16 0 0x1f 0 0x82 0x3f02\n"
" pci_write16 0 0x1f 0 0x82 0x3d01\n"
"";